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GR533x Datasheet

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V1.2

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文档中心 > GR533x Datasheet/ System/ Registers/ Always-on Control Copy URL

Always-on Control

MCU_CLK_CTRL

Name: MCU_CLK_CTRL Register
Description: MCU_CLK_CTRL Register
Base Address: 0x4000A000
Offset: 0x0
Reset Value: 0x42040202

Table 65 MCU_CLK_CTRL Register
Bits	Field Name	RW	Reset	Description
31	RSVD	R	0x0	Reserved bit
30	RNG_2MHZ_CLK_EN	RW	0x1	Enable/Disable RNG 256 KHz OSC CLK in PMU.
29	RSVD	R	0x0	Reserved bit
28:27	SLOW_CLK_SEL	RW	0x0	Select the source of aon_slow CLK. Please allow about 10 μs for switching. Value: 0x0: 256K RNG OSC CLK 0x1: 32K RNG OSC CLK 0x2: RC OSC 32K CLK 0x3: RTC OSC 32K CLK
26:24	SYS_CLK_RD	R	0x2	Current MCU_CLK_CTRL_SEL value
23:19	RSVD	R	0x0	Reserved bits
18:16	SER_CLK_SEL	RW	0x4	Select the clock for serial modules (UART, I2C, SPI_M, and SPI_S). Value: 0x0: 64M_clk PLL/HF_OSC 64 MHz CLK 0x1: 32M_clk PLL/HF_OSC 32 MHz CLK 0x2: 16M_clk PLL/HF_OSC 16 MHz CLK 0x3: 8M_clk PLL/HF_OSC 8 MHz CLK 0x4: XO_16M_clk XO 16 MHz CLK
15:13	RSVD	R	0x0	Reserved bits
12	WKUP_CLK_EN	RW	0x0	Apply WKUP_CLK_SEL to MCU_CLK_CTRL_SEL on wakeup.
11	RSVD	R	0x0	Reserved bit
10:8	WKUP_CLK_SEL	RW	0x2	Select system clock on wakeup. Value: 0x0: 64M_clk PLL/HF_OSC 64 MHz CLK 0x1: 32M_clk PLL/HF_OSC 32 MHz CLK 0x2: XO_16M_clk XO 16 MHz CLK 0x3: 16M_clk PLL/HF_OSC 16 MHz CLK 0x4: 8M_clk PLL/HF_OSC 8 MHz CLK 0x5: 2M_clk PLL/HF_OSC 2 MHz CLK
7:6	RSVD	R	0x0	Reserved bits
5:4	SLOW_CLK_CTRL_SEL	RW	0x0	Select WD timer, sleep timer, and RTC clock. Value: 0x0: RNG 32 kHz CLK 0x1: RNG 32 kHz CLK 0x2: RC 32 kHz CLK 0x3: RTC 32 kHz CLK
3	RSVD	R	0x0	Reserved bit
2:0	MCU_CLK_CTRL_SEL	RW	0x2	Select the system clock for MCU subsystem. Value: 0x0: 64M_clk PLL/HF_OSC 64 MHz CLK 0x1: 32M_clk PLL/HF_OSC 32 MHz CLK 0x2: XO_16M_clk XO 16 MHz CLK 0x3: 16M_clk PLL/HF_OSC 16 MHz CLK 0x4: 8M_clk PLL/HF_OSC 8 MHz CLK 0x5: 2M_clk PLL/HF_OSC 2 MHz CLK

MCU_MISC_CFG

Name: MCU_MISC_CFG Register
Description: MCU_MISC_CFG Register
Base Address: 0x4000A000
Offset: 0x4
Reset Value: 0x00000000

Table 66 MCU_MISC_CFG Register
Bits	Field Name	RW	Reset	Description
31:9	RSVD	R	0x0	Reserved bits
8	SWD_ENABLE	RW	0x0	Enable SWD debugging.
7:0	RSVD	R	0x0	Reserved bits

XO_CTRL

Name: XO_CTRL Register
Description: XO_CTRL Register
Base Address: 0x4000A000
Offset: 0x8
Reset Value: 0x00000100

Table 67 XO_CTRL Register
Bits	Field Name	RW	Reset	Description
31:25	RSVD	R	0x0	Reserved bits
24	BYP	RW	0x0	RF control register. Keep the default setting in test mode. Value: 0x0: Use the analog XO module. 0x1: Bypass the analog XO module. If the system uses XO or CPLL clock, an external oscillator shall be used.
23:9	RSVD	R	0x0	Reserved bits
8	2MHZ_ENA	RW	0x1	Enable XO 2 MHz from RF.
7:1	RSVD	R	0x0	Reserved bits
0	2MHZ_OUT	RW	0x0	Value: 0x0: normal aon_gpio[5] 0x1: aon_gpio[5] becomes xo_2mhz output.

FLASH_CACHE_CTRL0

Name: FLASH_CACHE_CTRL0 Register
Description: FLASH_CACHE_CTRL0 Register
Base Address: 0x4000A000
Offset: 0xC
Reset Value: 0x00000014

Table 68 FLASH_CACHE_CTRL0 Register
Bits	Field Name	RW	Reset	Description
31:9	RSVD	R	0x0	Reserved bits
8	XF_TAG_RET	RW	0x0	This signal controls and disables flushing of the tag memory on power-on: Value: 0x0: The tag memory will be flushed when mcu core is powered on. 0x1: Disable flushing the tag memory on mcu core power-on.
7:5	RSVD	R	0x0	Reserved bits
4	XF_XO_DIV1	RW	0x1	Always need to be set to 1.
3	RSVD	R	0x0	Reserved bit
2:0	XF_SCK_CLK_SEL	RW	0x4	XQSPI clock Value: 0x0: PLL 64 MHz 0x1: PLL 48 MHz 0x2: PLL 32 MHz 0x3: PLL 16 MHz 0x4: XO 16 MHz

FLASH_CACHE_CTRL1

Name: FLASH_CACHE_CTRL1 Register
Description: FLASH_CACHE_CTRL1 Register
Base Address: 0x4000A000
Offset: 0x10
Reset Value: 0x00000006

Table 69 FLASH_CACHE_CTRL1 Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	PAD_BYPASS	RW	0x1	Value: 0x0: the power of external Flash is controlled by HW automatically. 0x1: the power of external Flash is controlled by software.
1	RSVD	R	0x1	Reserved bit
0	PAD_EN	RW	0x0	External Flash pad is enabled by SW. This configuration takes effect only when the bypass_pwr_req signal is equal to 1'b1. Enable it to provide POWER to External Flash.

DIGIO_FST_CLK

Name: DIGIO_FST_CLK Register
Description: DIGIO_FST_CLK Register
Base Address: 0x4000A000
Offset: 0x14
Reset Value: 0x00000000

Table 70 DIGIO_FST_CLK Register
Bits	Field Name	RW	Reset	Description
31:9	RSVD	R	0x0	Reserved bits
8	SEL	RW	0x0	Clock for digital IO LDO Value: 0x0: 8 MHz 0x1: 16 MHz
7:1	RSVD	R	0x0	Reserved bits
0	EN	RW	0x0	Enable digital IO LDO fast CLK.

AON_CLK

Name: AON_CLK Register
Description: AON_CLK Register
Base Address: 0x4000A000
Offset: 0x18
Reset Value: 0x00000000

Table 71 AON_CLK Register
Bits	Field Name	RW	Reset	Description
31:9	RSVD	R	0x0	Reserved bits
8	WAKUP_FAST_CLK_SEL	RW	0x0	Select the source of the 192 MHz clock: Value: 0x0: cpll_clk 0x1: hf_osc_clk
7:5	RSVD	R	0x0	Reserved bits
4	WAKUP_CLK_EN	RW	0x0	Apply WAKUP_FAST_CLK_SEL value to CAL_FST_CLK on wakeup.
3:1	RSVD	R	0x0	Reserved bits
0	CAL_FST_CLK	RW	0x0	Select the source of the 192 MHz clock: Value: 0x0: cpll_clk 0x1: hf_osc_clk

TPP_ANA

Name: TPP_ANA Register
Description: TPP_ANA Register
Base Address: 0x4000A000
Offset: 0x20
Reset Value: 0x00000101

Table 72 TPP_ANA Register
Bits	Field Name	RW	Reset	Description
31:9	RSVD	R	0x0	Reserved bits
8	EN_N_RD	R	0x1	Actual value of EN_N
7:1	RSVD	R	0x0	Reserved bits
0	EN_N	RW	0x1	This register only gets reset through POR.

AON_PWR_SAVING

Name: AON_PWR_SAVING Register
Description: AON_PWR_SAVING Register
Base Address: 0x4000A000
Offset: 0x24
Reset Value: 0x00000000

Table 73 AON_PWR_SAVING Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R	0x0	Reserved bits
0	EN	RW	0x0	Set it to 1 to save more AON power.

MCU_WAKEUP_CTRL

Name: MCU_WAKEUP_CTRL Register
Description: MCU_WAKEUP_CTRL Register
Base Address: 0x4000A000
Offset: 0x80
Reset Value: 0x0000007F

Table 74 MCU_WAKEUP_CTRL Register
Bits	Field Name	RW	Reset	Description
31:7	RSVD	R	0x0	Reserved bits
6	COMP_FALL	RW	0x1	Select COMP_FALL IRQ as the wakeup event. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
5	AON_WDT	RW	0x1	Select AON_WDT IRQ as the wakeup event. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
4	COMP_RISE	RW	0x1	Select COMP_RISE IRQ as the wakeup event. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
3	RTC0	RW	0x1	Select RTC0 IRQ as the wakeup event. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
2	SMS_OSC	RW	0x1	Select SMS_OSC IRQ as the wakeup event. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
1	EXT	RW	0x1	Select EXT IRQ as the wakeup event. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
0	SLP_TIMER	RW	0x1	Select SLP_TIMER IRQ as the wakeup event. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.

AON_SLP_EVENT

Name: AON_SLP_EVENT Register
Description: AON_SLP_EVENT Register
Base Address: 0x4000A000
Offset: 0x84
Reset Value: 0x00000000

Table 75 AON_SLP_EVENT Register
Bits	Field Name	RW	Reset	Description
31:7	RSVD	R	0x0	Reserved bits
6	COMP_FALL	WC	0x0	COMP_FALL event that happened during sleeping or in functional mode. Write 0 to clear.
5	AON_WDT	WC	0x0	AON_WDT event that happened during sleeping or in functional mode. Write 0 to clear.
4	COMP_RISE	WC	0x0	COMP_RISE event that happened during sleeping or in functional mode. Write 0 to clear.
3	RTC0	WC	0x0	RTC0 event that happened during sleeping or in functional mode. Write 0 to clear.
2	SMS_OSC	WC	0x0	SMS_OSC event that happened during sleeping or in functional mode. Write 0 to clear.
1	EXT	WC	0x0	EXT event that happened during sleeping or in functional mode. Write 0 to clear.
0	SLP_TIMER	WC	0x0	SLP_TIMER event that happened during sleeping or in functional mode. Write 0 to clear.

AON_SLP_EVENT_RAW

Name: AON_SLP_EVENT_RAW Register
Description: AON_SLP_EVENT_RAW Register
Base Address: 0x4000A000
Offset: 0x8C
Reset Value: 0x00000000

Table 76 AON_SLP_EVENT_RAW Register
Bits	Field Name	RW	Reset	Description
31:7	RSVD	R	0x0	Reserved bits
6	PMU_COMP	R	0x0	AON sleep event status before masking (MCU_WAKEUP_CTRL). The bit order matches the AON_SLP_EVT register.
5	AON_WDT	R	0x0	AON Sleep event status before masking (MCU_WAKEUP_CTRL). The bit order matches the AON_SLP_EVT register.
4	PMU_MSIO	R	0x0	AON Sleep event status before masking (MCU_WAKEUP_CTRL). The bit order matches the AON_SLP_EVT register.
3	RTC0	R	0x0	AON Sleep event status before masking (MCU_WAKEUP_CTRL). The bit order matches the AON_SLP_EVT register.
2	SMS_OSC	R	0x0	AON Sleep event status before masking (MCU_WAKEUP_CTRL). The bit order matches the AON_SLP_EVT register.
1	EXT	R	0x0	AON Sleep event status before masking (MCU_WAKEUP_CTRL). The bit order matches the AON_SLP_EVT register.
0	SLP_TIMER	R	0x0	AON Sleep event status before masking (MCU_WAKEUP_CTRL). The bit order matches the AON_SLP_EVT register.

AON_IRQ

Name: AON_IRQ Register
Description: AON_IRQ Register
Base Address: 0x4000A000
Offset: 0x98
Reset Value: 0x00000008

Table 77 AON_IRQ Register
Bits	Field Name	RW	Reset	Description
31:7	RSVD	R	0x0	Reserved bits
6	SLP_FAIL_IRQ	WC	0x1	Sleep failure status. Write 0 to clear.
5	BLE_MAC_IRQ	WC	0x1	Bluetooth LE MAC IRQ status. Write 0 to clear.
4	PMU_BOD_FALL	WC	0x1	PMU BOD falling edge IRQ status. Write 0 to clear.
3	AONPLL_CHG	WC	0x1	PLL power-on done IRQ status. Write 0 to clear.
2	PMU_BOD_RISE	WC	0x1	BOD rising edge IRQ status. Write 0 to clear.
1	BLE_PWR_DN	WC	0x1	Bluetooth LE power-off done IRQ status. Write 0 to clear.
0	BLE_PWR	WC	0x1	Bluetooth LE power-on done IRQ status. Write 0 to clear.

AON_IRQ_EN

Name: AON_IRQ_EN Register
Description: AON_IRQ_EN Register
Base Address: 0x4000A000
Offset: 0x9C
Reset Value: 0x000000FF

Table 78 AON_IRQ_EN Register
Bits	Field Name	RW	Reset	Description
31:7	RSVD	R	0x0	Reserved bits
6	SLP_FAIL_IRQ	RW	0x1	Enable sleep failure status. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
5	BLE_MAC_IRQ	RW	0x1	Enable Bluetooth LE MAC IRQ. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
4	PMU_BOD_FALL	RW	0x1	Enable PMU BOD falling edge IRQ. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
3	AONPLL_CHG	RW	0x1	Enable PLL power-on done IRQ. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
2	PMU_BOD_RISE	RW	0x1	Enable BOD rising edge IRQ. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
1	BLE_PWR_DN	RW	0x1	Enable Bluetooth LE power-off done IRQ. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.
0	BLE_PWR_ON	RW	0x1	Enable Bluetooth LE power-on done IRQ. Value: 0x0: Disable IRQ. 0x1: Enable IRQ.

AON_DBG_CTRL

Name: AON_DBG_CTRL Register
Description: AON_DBG_CTRL Register
Base Address: 0x4000A000
Offset: 0xA8
Reset Value: 0x00000007

Table 79 AON_DBG_CTRL Register
Bits	Field Name	RW	Reset	Description
31:17	RSVD	R	0x0	Reserved bits
16	DBG_SLP	RW	0x0	Prevent sleep when JLINK is attached.
15:3	RSVD	R	0x0	Reserved bits
2	AON_WDT	RW	0x1	Set to stop the watchdog timer when MCU halts.
1	RTC	RW	0x1	Set to stop the calendar timer when MCU halts.
0	SLP_TIMER	RW	0x1	Set to stop the sleep timer when MCU halts.

MEM_MARGIN

Name: MEM_MARGIN Register
Description: MEM_MARGIN Register
Base Address: 0x4000A000
Offset: 0x1C0
Reset Value: 0x000000CC

Table 80 MEM_MARGIN Register
Bits	Field Name	RW	Reset	Description
31:8	RSVD	R	0x0	Reserved bits
7:6	NON_CRITICAL_MEM_RWM	RW	0x3	Control of non-critical memory margin adjustment
5	NON_CRITICAL_MEM_WM	RW	0x0	Write margin adjustment of non-critical memory
4	NON_CRITICAL_MEM_RM	RW	0x0	Read margin adjustment of non-critical memory
3:2	CRITICAL_MEM_RWM	RW	0x3	Control of critical memory margin adjustment
1	CRITICAL_MEM_WM	RW	0x0	Write margin adjustment of critical memory
0	CRITICAL_MEM_RM	RW	0x0	Read margin adjustment of critical memory

MEM_PARAM

Name: MEM_PARAM Register
Description: MEM_PARAM Register
Base Address: 0x4000A000
Offset: 0x1C4
Reset Value: 0x00000008

Table 81 MEM_PARAM Register
Bits	Field Name	RW	Reset	Description
31:4	RSVD	R	0x0	Reserved bits
3:0	MEM_BTRM	RW	0x8	Source Bias Trim Adjustment for all SRAMs

EXT_WAKEUP_CTRL0

Name: EXT_WAKEUP_CTRL0 Register
Description: EXT_WAKEUP_CTRL0 Register
Base Address: 0x4000A000
Offset: 0x200
Reset Value: 0x00000000

Table 82 EXT_WAKEUP_CTRL0 Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R	0x0	Reserved bits
15:8	INVERT	RW	0x0	Invert external wakeup. bit7: aon_gpio7 bit6: aon_gpio6 bit5: aon_gpio5 bit4: aon_gpio4 bit3: aon_gpio3 bit2: aon_gpio2 bit1: aon_gpio1 bit0: aon_gpio0 Value: 0x0: Do not invert 0x1: Invert
7:0	SRC_EN	RW	0x0	Enable external wakeup source. bit7: aon_gpio7 bit6: aon_gpio6 bit5: aon_gpio5 bit4: aon_gpio4 bit3: aon_gpio3 bit2: aon_gpio2 bit1: aon_gpio1 bit0: aon_gpio0 Value: 0x0: Disable 0x1: Enable

EXT_WAKEUP_CTRL1

Name: EXT_WAKEUP_CTRL1 Register
Description: EXT_WAKEUP_CTRL1 Register
Base Address: 0x4000A000
Offset: 0x204
Reset Value: 0x00000000

Table 83 EXT_WAKEUP_CTRL1 Register
Bits	Field Name	RW	Reset	Description
31:24	RSVD	R	0x0	Reserved bits
23:16	EDGE_BOTH	RW	0x0	Valid when EDGE_EN = 1 bit7: aon_gpio7 bit6: aon_gpio6 bit5: aon_gpio5 bit4: aon_gpio4 bit3: aon_gpio3 bit2: aon_gpio2 bit1: aon_gpio1 bit0: aon_gpio0 Value: 0x0: single edge 0x1: both edges
15:8	EDGE_TYPE	RW	0x0	Valid when EDGE_EN = 1 & EDGE_BOTH = 0 bit7: aon_gpio7 bit6: aon_gpio6 bit5: aon_gpio5 bit4: aon_gpio4 bit3: aon_gpio3 bit2: aon_gpio2 bit1: aon_gpio1 bit0: aon_gpio0 Value: 0x0: rising edge 0x1: falling edge
7:0	EDGE_EN	RW	0x0	Enable edge detecting. bit7: aon_gpio7 bit6: aon_gpio6 bit5: aon_gpio5 bit4: aon_gpio4 bit3: aon_gpio3 bit2: aon_gpio2 bit1: aon_gpio1 bit0: aon_gpio0 Value: 0x0: level signal 0x1: Detect the edge.

EXT_WAKEUP_STAT

Name: EXT_WAKEUP_STAT Register
Description: EXT_WAKEUP_STAT Register
Base Address: 0x4000A000
Offset: 0x20C
Reset Value: 0x00000000

Table 84 EXT_WAKEUP_STAT Register
Bits	Field Name	RW	Reset	Description
31:8	RSVD	R	0x0	Reserved bits
7:0	STAT	WC	0x0	External wakeup status (after masking). Write 0 to clear the wakeup status (both level and pulse). bit7: aon_gpio7 bit6: aon_gpio6 bit5: aon_gpio5 bit4: aon_gpio4 bit3: aon_gpio3 bit2: aon_gpio2 bit1: aon_gpio1 bit0: aon_gpio0 Value: 0x0: not triggered 0x1: triggered

COMM_CTRL

Name: COMM_CTRL Register
Description: COMM_CTRL Register
Base Address: 0x4000A000
Offset: 0x280
Reset Value: 0x00020000

Table 85 COMM_CTRL Register
Bits	Field Name	RW	Reset	Description
31:18	RSVD	R	0x0	Reserved bits
17:16	TIMER_CLK_SEL	RW	0x2	Select Comm timer clock. Value: 0x0: rtc_osc_clk 0x1: rng_2_osc_clk (rc32k) 0x2: rng_osc_clk
15:10	RSVD	R	0x0	Reserved bits
9	DEEPSLCNTL_EXTWKUPDSB	R	0x0	Comm timer register
8	DEEPSLCNTL_SOFT_WAKEUP_REQ	R	0x0	Comm timer register
7	RSVD	R	0x0	Reserved bit
6	DEEPSLCNTL_DEEP_SLEEP_ON	R	0x0	Comm timer register
5	DEEPSLCNTL_RADIO_SLEEP_EN	R	0x0	Comm timer register
4	DEEPSLCNTL_OSC_SLEEP_EN	R	0x0	Comm timer register
3	RSVD	R	0x0	Reserved bit
2	DEEPSLCNTL_DEEP_SLEEP_STAT	R	0x0	Comm timer register
1:0	RSVD	R	0x0	Reserved bits

BLE_MISC

Name: BLE_MISC Register
Description: BLE_MISC Register
Base Address: 0x4000A000
Offset: 0x284
Reset Value: 0x00000000

Table 86 BLE_MISC Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R	0x0	Reserved bits
0	SMC_WAKEUP_REQ	RW	0x0	Wake up SMC by MCU; it needs to be cleared by MCU as well.

COMM_TIMER_CFG0

Name: COMM_TIMER_CFG0 Register
Description: COMM_TIMER_CFG0 Register
Base Address: 0x4000A000
Offset: 0x288
Reset Value: 0x00000000

Table 87 COMM_TIMER_CFG0 Register
Bits	Field Name	RW	Reset	Description
31:0	DEEPSLWKUP	RW	0x0	Used for Comm timer

COMM_TIMER_CFG1

Name: COMM_TIMER_CFG1 Register
Description: COMM_TIMER_CFG1 Register
Base Address: 0x4000A000
Offset: 0x28C
Reset Value: 0x00000000

Table 88 COMM_TIMER_CFG1 Register
Bits	Field Name	RW	Reset	Description
31:0	ENBPRESET	RW	0x0	Used for Comm timer

BLE_DEEP_SLP_CORR_EN

Name: BLE_DEEP_SLP_CORR_EN Register
Description: BLE_DEEP_SLP_CORR_EN Register
Base Address: 0x4000A000
Offset: 0x290
Reset Value: 0x00000001

Table 89 BLE_DEEP_SLP_CORR_EN Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1	HW_EN	RW	0x0	Enable HW Timer Correction Operation.
0	FW_EN	RW	0x1	Enable FW Timer Correction Operation.

BLE_DEEP_SLP_HW_TIMER_CORR

Name: BLE_DEEP_SLP_HW_TIMER_CORR Register
Description: BLE_DEEP_SLP_HW_TIMER_CORR Register
Base Address: 0x4000A000
Offset: 0x294
Reset Value: 0x0F424000

Table 90 BLE_DEEP_SLP_HW_TIMER_CORR Register
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R	0x0	Reserved bits
29:12	RTC_TOSC	RW	0XF424	Period of RTC clock in μs
11:10	RSVD	R	0x0	Reserved bits
9:0	WAIT	RW	0x0	Wait time in μs after wakeup before correction begins

COMM_TIMER_STAT

Name: COMM_TIMER_STAT Register
Description: COMM_TIMER_STAT Register
Base Address: 0x4000A000
Offset: 0x298
Reset Value: 0x00000000

Table 91 COMM_TIMER_STAT Register
Bits	Field Name	RW	Reset	Description
31:0	DEEPSLSTAT	RW	0x0	Sleep status

PMU_COMP_GLITCH_REMOVE

Name: PMU_COMP_GLITCH_REMOVE Register
Description: PMU_COMP_GLITCH_REMOVE Register
Base Address: 0x4000A000
Offset: 0x2C0
Reset Value: 0x00000000

Table 92 PMU_COMP_GLITCH_REMOVE Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2:0	CYCLE	RW	0x0	Value: 0x0: no digital de-glitch Others: The de-glitch step is the clock cycle of aon_slow_clk (32K/256K).

SOFTWARE_REG0

Name: SOFTWARE_REG0 Register
Description: SOFTWARE_REG0 Register
Base Address: 0x4000A000
Offset: 0x340
Reset Value: 0x00000000

Table 93 SOFTWARE_REG0 Register
Bits	Field Name	RW	Reset	Description
31:0	SOFTWARE_REG0	RW	0x0	Used to save some values which can be used after waking up

SOFTWARE_REG1

Name: SOFTWARE_REG1 Register
Description: SOFTWARE_REG1 Register
Base Address: 0x4000A000
Offset: 0x344
Reset Value: 0x00000000

Table 94 SOFTWARE_REG1 Register
Bits	Field Name	RW	Reset	Description
31:0	SOFTWARE_REG1	RW	0x0	Used to save some values which can be used after waking up

SLP_BUSY_STAT

Name: SLP_BUSY_STAT Register
Description: SLP_BUSY_STAT Register
Base Address: 0x4000A000
Offset: 0x348
Reset Value: 0x00000000

Table 95 SLP_BUSY_STAT Register
Bits	Field Name	RW	Reset	Description
31:17	RSVD	R	0x0	Reserved bits
16:0	SLP_BUSY_STS	R	0x0	Sleep busy status, which is updated when sleep fails bit16: rng_busy bit15: uart_0_busy bit14: uart_1_busy bit13: spi_m_busy bit12: spi_s_busy bit11: i2c_0_busy bit10: i2c_1_busy bit9: pwm_0_busy bit8: pwm_1_busy bit7: mcu_dualtimer_busy bit6: mcu_apb_timer_0_busy bit5: mcu_apb_timer_1_busy bit4: snadc_busy bit3: dma_busy bit2: clk_calib_0_busy bit1: clk_calib_1_busy bit0: ble_pwr_off_busy

SLP_BUSY_BYPASS

Name: SLP_BUSY_BYPASS Register
Description: SLP_BUSY_BYPASS Register
Base Address: 0x4000A000
Offset: 0x34C
Reset Value: 0x0001FFFF

Table 96 SLP_BUSY_BYPASS Register
Bits	Field Name	RW	Reset	Description
31:17	RSVD	R	0x0	Reserved bits
16:0	SLP_BUSY_BYPASS	RW	0x1FFFF	0x1: Bypass HW auto goto sleep function. bit16: Bypass the rng_busy. bit15: Bypass the uart_0_busy. bit14: Bypass the uart_1_busy. bit13: Bypass the spi_m_busy. bit12: Bypass the spi_s_busy. bit11: Bypass the i2c_0_busy. bit10: Bypass the i2c_1_busy. bit9: Bypass the pwm_0_busy. bit8: Bypass the pwm_1_busy. bit7: Bypass the mcu_dualtimer_busy. bit6: Bypass the mcu_apb_timer_0_busy. bit5: Bypass the mcu_apb_timer_1_busy. bit4: Bypass the snadc_busy. bit3: Bypass the dma_busy. bit2: Bypass the clk_calib_0_busy. bit1: Bypass the clk_calib_1_busy. bit0: Bypass the ble_pwr_off_busy.

DBG_REG0

Name: DBG_REG0 Register
Description: DBG_REG0 Register
Base Address: 0x4000A000
Offset: 0x380
Reset Value: 0x00000000

Table 97 DBG_REG0 Register
Bits	Field Name	RW	Reset	Description
31:15	RSVD	R	0x0	Reserved bits
14:13	DBG_FLAGSELH	RW	0x0	Value: 0x0: Output high 8 bits tie to 8'h0. 0x1: Select flag_in01 high 8 bits. 0x2: Select flag_in02 high 8 bits.
12	DBG_FLAGH_EN	RW	0x0	Value: 0x0: Disable high block of debug bus. 0x1: Enable high block of debug bus.
11	RSVD	R	0x0	Reserved bit
10:9	DBG_FLAGSELL	RW	0x0	Value: 0x0: Output low 8 bits tie to 8'h0. 0x1: Select flag_in01 low 8 bits. 0x2: Select flag_in02 low 8 bits.
8	DBG_FLAGL_EN	RW	0x0	Value: 0x0: Disable low block of debug bus. 0x1: Enable low block of debug bus.
7:4	DBG_BUS_SEL	RW	0x0	bit0: debug bus to AON pads Value: 0x0: Disable debug bus. 0x1: Enable debug bus. bit1: Value: 0x0: Select low 8 bits to AON pads. 0x1: Select high 8 bits connected to AON pads. bit2: debug bus to MISO pads Value: 0x0: Disable debug bus. 0x1: Enable debug bus. bit3: Value: 0x0: Select low 10 bits to MSIO pads. 0x1: Select high 10 bits connected to MSIO pads.
3:1	RSVD	R	0x0	Reserved bits
0	DBG_SYS_CLK_SEL	RW	0x0	0x1: Use the test logic to generate the final MCU_CLK_CTRL_SEL.

DBG_REG_RST_SRC

Name: DBG_REG_RST_SRC Register
Description: DBG_REG_RST_SRC Register
Base Address: 0x4000A000
Offset: 0x384
Reset Value: 0x01010030

Table 98 DBG_REG_RST_SRC Register
Bits	Field Name	RW	Reset	Description
31	CFG	W	0x0	Write 1 to apply the bit [25:24].
30	CFG_BUSY	R	0x0	0x1: The block is being configured. Do not perform any write operation.
29:25	RSVD	R	0x0	Reserved bits
24	EN	RW	0x1	1: Enable reset source record.
23:15	RSVD	R	0x0	Reserved bits
16	RDY	R	0x1	Value: 0x0: The block is not ready to record. 0x1: The block is ready to record.
15:6	RSVD	R	0x0	Reserved bits
5:0	STS	WC	0x30	Reset season status: Bit 0: System reset. Clear the bit by writing 1 to it. Bit 1: System watchdog reset. Clear the bit by writing 1 to it. Bit 2: AON watchdog reset. Clear the bit by writing 1 to it. Bit 3: System full reset. Clear the bit by writing 1 to it. Bit 4: POR reset. Clear the bit by writing 1 to it. Bit 5: Sleep reset. Clear the bit by 1" to it.

MEM_BOND_OPT_REG

Name: MEM_BOND_OPT_REG Register
Description: MEM_BOND_OPT_REG Register
Base Address: 0x4000A000
Offset: 0x3A0
Reset Value: 0x00000000

Table 99 MEM_BOND_OPT_REG Register
Bits	Field Name	RW	Reset	Description
31:16	REG_MAGIC_WORD	W	0x0	The valid magic word is 16h5A5A. BOND_OPT cannot be written except when the magic word is valid.
15:2	RSVD	R	0x0	Reserved bits
1:0	BOND_OPT	RW	0x0	Value: 0x0: 96 KB (SRAMs 0–5 ON) 0x1: 80 KB (SRAMs 0–4 ON; SRAM 5 OFF) 0x2: 64 KB (SRAMs 0–3 ON; SRAMs 4–5 OFF) 0x3: 48 KB (SRAMs 0–2 ON; SRAMs 3–5 OFF)

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