eFuse
TPGM
- Name: TPGM Register
- Description: TPGM Register
- Base Address: 0x40018400
- Offset: 0x0
- Reset Value: 0x00010281
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:20 |
RSVD |
R |
0x0 |
Reserved bits |
19:12 |
WRITE_INTERVAL |
RW |
0x10 |
Interval between two bits in eFuse, number of APB CLK cycles. |
11:0 |
TIME |
RW |
0x281 |
eFuse programming time, tpro = TIME*T, where T is clock period; typically tpro = 10000 ns, and 9000 ns < tpro < 11000 ns |
PGENB
- Name: PGENB Register
- Description: PGENB Register
- Base Address: 0x40018400
- Offset: 0x4
- Reset Value: 0x00000001
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
0x0 |
Reserved bits |
0 |
SIG |
RW |
0x1 |
eFuse programming enable signal control (active low) Value:
|
OPERATION
- Name: OPERATION Register
- Description: OPERATION Register
- Base Address: 0x40018400
- Offset: 0x8
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
0x0 |
Reserved bits |
0 |
INIT_CHECK |
W |
0x0 |
Writing "1" to this bit enables eFuse ctrl to start to read the whole eFuse value; at the same time, check this value with "0". |
STAT
- Name: STAT Register
- Description: STAT Register
- Base Address: 0x40018400
- Offset: 0xC
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
0x0 |
Reserved bits |
2 |
WRITE_DONE |
RC |
0x0 |
eFuse one word write done Note: Reading this register enables hardware to clear this bit. |
1 |
INIT_SUCCESS |
RC |
0x0 |
eFuse initial value check success means the eFuse values are all "0". Note: Reading this register enables hardware to clear this bit. |
0 |
INIT_DONE |
RC |
0x0 |
eFuse initial value check done Note: Reading this register enables hardware to clear this bit. |
