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GR533x Datasheet

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V1.2

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文档中心 > GR533x Datasheet/ System/ Registers/ Clock Calibration Copy URL

Clock Calibration

SL_CLK_CTRL

Name: SL_CLK_CTRL Register
Description: This register enables SL clock calibration.
Base Address: 0x4000E400
Offset: 0x0
Reset Value: 0x00000000

Table 222 SL_CLK_CTRL Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R	0x0	Reserved bits
0	EN	RW	0x0	Enable clock calibration block. Value: 0x1: Enable the block. 0x0: Disable the block.

SL_CLK_CNT

Name: SL_CLK_CNT Register
Description: This register sets the number of cycles of the slow clock.
Base Address: 0x4000E400
Offset: 0x4
Reset Value: 0x00000000

Table 223 SL_CLK_CNT Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R	0x0	Reserved bits
11:0	COUNT	RW	0x0	Number of cycles of the slow clock

SL_CLK_STAT

Name: SL_CLK_STAT Register
Description: This register indicates the calibration status.
Base Address: 0x4000E400
Offset: 0x8
Reset Value: 0x00000000

Table 224 SL_CLK_STAT Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1	OVER	R	0x0	Fast clock counter overflow. Need to reduce slow clock cnt_val.
0	DONE	R	0x0	Calibration done status

SL_CLK_CNT0

Name: SL_CLK_CNT0 Register
Description: This register sets the fast clock counter value.
Base Address: 0x4000E400
Offset: 0xC
Reset Value: 0x00000000

Table 225 SL_CLK_CNT0 Register
Bits	Field Name	RW	Reset	Description
31:24	RSVD	R	0x0	Reserved bits
23:0	VAL	R	0x0	Fast clock counter value

SL_CLK_CNT1

Name: SL_CLK_CNT1 Register
Description: This register reads the current counter value of the slow clock.
Base Address: 0x4000E400
Offset: 0x10
Reset Value: 0x00000000

Table 226 SL_CLK_CNT1 Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R	0x0	Reserved bits
11:0	VAL	R	0x0	Read the current counter value of the slow clock.

SL_CLK_INT_EN

Name: SL_CLK_INT_EN Register
Description: This register enables the clock interrupt.
Base Address: 0x4000E400
Offset: 0x14
Reset Value: 0x00000003

Table 227 SL_CLK_INT_EN Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1	OVER	RW	0x1	Interrupt Enable ONLY. The status in CLK_STAT can be read no matter whether the interrupt is enabled.
0	DONE	RW	0x1	Interrupt Enable ONLY. The status in CLK_STAT can be read no matter whether the interrupt is enabled.

SL_CLK_INT_CLR

Name: SL_CLK_INT_CLR Register
Description: This register clears the clock interrupt.
Base Address: 0x4000E400
Offset: 0x18
Reset Value: 0x00000000

Table 228 SL_CLK_INT_CLR Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1	OVER	W	0x0	Write the corresponding bit to clear the interrupt.
0	DONE	W	0x0	Write the corresponding bit to clear the interrupt.

SL_CLK_SEL

Name: SL_CLK_SEL Register
Description: This register selects the slow clock source.
Base Address: 0x4000E400
Offset: 0x20
Reset Value: 0x00000000

Table 229 SL_CLK_SEL Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1:0	SLOW_CLK_SEL	RW	0x0	Select slow clock source. Only valid for the defined source value Value: 0x0: LFXO_32K 0x1: LFRC_32K 0x2: RNG_32K from RNG_OSC

HS_CLK_CTRL

Name: HS_CLK_CTRL Register
Description: This register enables HS clock calibration.
Base Address: 0x4000E400
Offset: 0x100
Reset Value: 0x00000000

Table 230 HS_CLK_CTRL Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R	0x0	Reserved bits
0	EN	RW	0x0	Enable clock calibration block. Value: 0x1: Enable the block. 0x0: Disable the block.

HS_CLK_CNT

Name: HS_CLK_CNT Register
Description: This register sets the number of cycles of the slow clock.
Base Address: 0x4000E400
Offset: 0x104
Reset Value: 0x00000000

Table 231 HS_CLK_CNT Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R	0x0	Reserved bits
11:0	COUNT	RW	0x0	Number of cycles of the slow clock

HS_CLK_STAT

Name: HS_CLK_STAT Register
Description: This register indicates the calibration status.
Base Address: 0x4000E400
Offset: 0x108
Reset Value: 0x00000000

Table 232 HS_CLK_STAT Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1	OVER	R	0x0	Fast clock counter overflow. Need to reduce slow clock cnt_val.
0	DONE	R	0x0	Calibration done status

HS_CLK_CNT0

Name: HS_CLK_CNT0 Register
Description: This register sets the fast clock counter value.
Base Address: 0x4000E400
Offset: 0x10C
Reset Value: 0x00000000

Table 233 HS_CLK_CNT0 Register
Bits	Field Name	RW	Reset	Description
31:24	RSVD	R	0x0	Reserved bits
23:0	VAL	R	0x0	Fast clock counter value

HS_CLK_CNT1

Name: HS_CLK_CNT1 Register
Description: This register reads the current counter value of the slow clock.
Base Address: 0x4000E400
Offset: 0x110
Reset Value: 0x00000000

Table 234 HS_CLK_CNT1 Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R	0x0	Reserved bits
11:0	VAL	R	0x0	Read the current counter value of the slow clock.

HS_CLK_INT_EN

Name: HS_CLK_INT_EN Register
Description: This register enables the clock interrupt.
Base Address: 0x4000E400
Offset: 0x114
Reset Value: 0x00000003

Table 235 HS_CLK_INT_EN Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1	OVER	RW	0x1	Interrupt Enable ONLY. The status in CLK_STAT can be read no matter whether the interrupt is enabled.
0	DONE	RW	0x1	Interrupt Enable ONLY. The status in CLK_STAT can be read no matter whether the interrupt is enabled.

HS_CLK_INT_CLR

Name: HS_CLK_INT_CLR Register
Description: This register clears the clock interrupt.
Base Address: 0x4000E400
Offset: 0x118
Reset Value: 0x00000000

Table 236 HS_CLK_INT_CLR Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1	OVER	W	0x0	Write the corresponding bit to clear the interrupt.
0	DONE	W	0x0	Write the corresponding bit to clear the interrupt.

HS_CLK_SEL

Name: HS_CLK_SEL Register
Description: This register selects the slow clock source.
Base Address: 0x4000E400
Offset: 0x120
Reset Value: 0x00000000

Table 237 HS_CLK_SEL Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1:0	SLOW_CLK_SEL	RW	0x0	Select slow clock source. Only valid for the defined source value Value: 0x0: LFXO_32K 0x1: LFRC_32K 0x2: XO_32K from XO_32M

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