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文档中心 > GR533x Datasheet/ System/ Registers/ Always-on PMU Control Copy URL

Always-on PMU Control

RF_REG_0

  • Name: RF_REG_0 Register
  • Description: RF_REG_0 Register
  • Base Address: 0x4000A800
  • Offset: 0x4
  • Reset Value: 0x08588E70
Table 131 RF_REG_0 Register
Bits Field Name RW Reset Description

31:24

IO_LDO_REG1

RW

0x8

[7] IO_LDO bypass mode

[6:0] Default is 1.8 V.

23:16

LPD_REG2

RW

0x58

[7] NC

[6:4] AON_LDO vref trimming/output options (0.75/0.80/0.85/0.90/0.95/1.0/1.05/1.1)

[3] Enable LPD BG static mode.

[2:0] LPD dynamic mode period option (frequency for clk_ph1/clk_ph2/clk_ph3)

15:8

LPD_REG1

RW

0x8E

[7:5] Temperature coefficient (Tempco) trimming

[4:2] RET_LDO vref trimming/output options (0.6/0.65/0.7/0.75/0.8/0.9/1.0/1.1)

[1] Enable Vret, which can be turned off during ultra deep sleep mode.

[0] NC

7:0

RTC_REG1

RW

0x70

[7] Enable RTC.

[6] NC. Enable Constant GM mode.

[5] NC

[4:0] GM control

RF_REG_1

  • Name: RF_REG_1 Register
  • Description: RF_REG_1 Register
  • Base Address: 0x4000A800
  • Offset: 0x8
  • Reset Value: 0x919A6F0F
Table 132 RF_REG_1 Register
Bits Field Name RW Reset Description
31:24 DCDC_REG4 RW 0x91

[7] Enable ZCS skip function.

[6:4] Change BUCK ZCS offset to positive.

[3:1] Change BUCK ZCS offset to negative.

[0] Enable ZCS skip function; NC
23:16 DCDC_REG3 RW 0x9A

[7:3] hi-bit = 0, 769 mV–1035 mV, 18 mV/step; hi-bit = 1, 1053 mV–1436 mV, 25 mV/step

[2:1] Control low limit of DC-DC switching frequency. 00/01: 842 kHz; 10:640 kHz; 11:516 kHz

[0] Enable frequency limit function.
15:8 DCDC_REG2 RW 0x6F

[7:3] Trim the internal OSC to 32M.

[2:0] Change the length of driver deadtime; the optimized value is 010.
7:0 DCDC_REG1 RW 0xF

[7] Enable BUCK state machine. 0: DC-DC pause working

[6] Select CLK source. 1: external; 0: internal. Warning: Do not switch before XO32M works normally.

[5] Enable BUCK test mode.

[4] 1: Use Vreg to operate DC-DC. 0: Use LDO to operate DC-DC.

[3:2] Change the number of BUCK NMOS driver.

[1:0] Change the number of BUCK PMOS driver.

RF_REG_2

  • Name: RF_REG_2 Register
  • Description: RF_REG_2 Register
  • Base Address: 0x4000A800
  • Offset: 0xC
  • Reset Value: 0x0084A0C0
Table 133 RF_REG_2 Register
Bits Field Name RW Reset Description
31:24 RSVD R 0x0 Reserved bits
23:16 PMU_BG_REG RW 0x84

[7:5] bandgap TC fine trimming. 3b'000: most negative

[4] NC

[3] Forcibly enable main BG when DC-DC and SYS are off.

[2:0] bandgap TC coarse trimming. 3b'000: most negative
15:8 GP_REG1 RW 0xA0

[7:5] reference control - default 101

[4] delayed enable signal for efuse_vddq (2.5 V)

[3] Enable eFuse 2.5 V.

[2] Enable eFuse 1.1 V.

[1] Bypass vddq to VBATL (when EN = 1).

[0] NC
7:0 MUX1_REG1 RW 0xC0

[7] en_mux_msio

[6] mux_en

[5:3] mux_a

[2:0] Block selection. 000 - Sense ADC; 001:

RF_REG_3

  • Name: RF_REG_3 Register
  • Description: RF_REG_3 Register
  • Base Address: 0x4000A800
  • Offset: 0x10
  • Reset Value: 0x11924729
Table 134 RF_REG_3 Register
Bits Field Name RW Reset Description

31:30

RSVD

R

0x0

 Reserved bits

29

BOD2_PWR_CTRL_POST

R

0x0

Real power state of BOD2

Value:

  • 0x0: OFF

  • 0x1: ON

28

BOD2_BYPASS

RW

0x1

Bypass the power-on and power-off of BOD2 automatically.

27

RSVD

R

0x0

 Reserved bits

26

COMP_INT

R

0x0

COMP interrupt

25

BOD2_INT

R

0x0

BOD interrupt

24

BOD2_OK

R

0x1

BOD works normally.

23:16

LPD_REG61

RW

0x92

[7] Enable STB_IO_LDO.

[6:5] STB_IO_LDO output options (1.8/2.5/3.3)

[4:3] 1.1 V LDO Vref trimming/output options (1.05/1.1/1.15/1.2)

[2:0] prebias IPAT current trimming

15:8

LPD_REG60

RW

0x47

[7:4] STB_IO_LDO Vref trimming

[3:1] 1.2 V Vref (for SIDO) trimming

[0] NC

7:6

RSVD

R

0x0

 Reserved bits

5

BOD_STATIC_EN

RW

0x1

The dynamic mode has lower power but lower accuracy.

Value:

  • 0x0: Enable dynamic mode.

  • 0x1: Enable static mode.

4:2

BOD2_LVL_CTRL_LV

RW

0x2

BOD2 level control bits

1

BOD2_EN

RW

0x0

Value:

  • 0x0: Disable BOD interrupt.

  • 0x1: Enable BOD interrupt.

0

BOD_EN

RW

0x1

Value:

  • 0x0: Disable BOD reset.

  • 0x1: Enable BOD reset.

RF_REG_4

  • Name: RF_REG_4 Register
  • Description: RF_REG_4 Register
  • Base Address: 0x4000A800
  • Offset: 0x14
  • Reset Value: 0x00230000
Table 135 RF_REG_4 Register
Bits Field Name RW Reset Description

31:24

RSVD

R

0x0

 Reserved bits

23:16

ANACORE_LDO_REG1

RW

0x23

[7] en_bleed

[6] Enable bypass mode.

[5:4] digcore_ldo_out, 0.8/0.9/1.0/(soft bypass)

[3] Bypass VDDaon to VDDcore.

[2] NC; test function; slowly start to prevent VBAT drop.

[1:0] NC; digcore_ldo_out trimming; defaulted to +10%, have been moved to overwrite register

15:0

RSVD

R

0x0

 Reserved bits

RC_RTC_REG_0

  • Name: RC_RTC_REG_0 Register
  • Description: RC_RTC_REG_0 Register
  • Base Address: 0x4000A800
  • Offset: 0x48
  • Reset Value: 0x900ADD8B
Table 136 RC_RTC_REG_0 Register
Bits Field Name RW Reset Description

31:24

RTC_CAP

RW

0x90

[7] FBresistor

[6] FBresistor

[5:0] cap control

23:16

RTC_CS

RW

0xA

[7] NC

[6] NC

[5] NC

[4:0] CS

15:8

RC_REG2

RW

0xDD

[7] Enable RCOSC.

[6] Enable RCOSC delay.

[5:3] RCOSC rdiv_delay_ctrl

[2:0] RCOSC resn_ctrl

7:0

RC_REG1

RW

0x8B

[7:6] RCOSC bias control

[5] cgm_byp

[4:3] NC

[2:0] NC

FS_REG_0

  • Name: FS_REG_0 Register
  • Description: FS_REG_0 Register
  • Base Address: 0x4000A800
  • Offset: 0x50
  • Reset Value: 0x00000000
Table 137 FS_REG_0 Register
Bits Field Name RW Reset Description

31:24

RSVD

R

0x0

 Reserved bits

23:16

FINE_CODE

RW

0x0

Fine code

15:0

RSVD

R

0x0

 Reserved bits

FS_REG_1

  • Name: FS_REG_1 Register
  • Description: FS_REG_1 Register
  • Base Address: 0x4000A800
  • Offset: 0x54
  • Reset Value: 0x00000A60
Table 138 FS_REG_1 Register
Bits Field Name RW Reset Description
31:16 RSVD R 0x0 Reserved bits
15:8 FS_REG5 RW 0xA

[7:5] NC

[4] test function; add zero in feedback loop.

[3:0] Control input reference voltage.
7:0 FS_REG4 RW 0x60

[7:6] ctrl_osc_fin

[5:4] NC

[3:0] coarse code that controls hf_clk frequency. Use the default: 0000 (Need one-time calibration using the on-chip frequency calibration).

PMU_TON_CFG

  • Name: PMU_TON_CFG Register
  • Description: PMU_TON_CFG Register
  • Base Address: 0x4000A800
  • Offset: 0x94
  • Reset Value: 0x00000606
Table 139 PMU_TON_CFG Register
Bits Field Name RW Reset Description

31:12

RSVD

R

0x0

 Reserved bits

11:8

OFF

RW

0x6

TON_CTRL value when TXEN = 0

7:4

RSVD

R

0x0

 Reserved bits

3:0

ON

RW

0x6

TON_CTRL value when TXEN = 1

PMU_INTF_OVR_EN_0

  • Name: PMU_INTF_OVR_EN_0 Register
  • Description: PMU_INTF_OVR_EN_0 Register
  • Base Address: 0x4000A800
  • Offset: 0xC0
  • Reset Value: 0x00000000
Table 140 PMU_INTF_OVR_EN_0 Register
Bits Field Name RW Reset Description

31:9

RSVD

R

0x0

 Reserved bits

8

AVS_CTL_REF_EN

RW

0x0

Value for AVS_CTL_REF overwrite interface

7

RNG_OSC_CLK_EN

RW

0x0

Value for RNG_OSC_CLK overwrite interface

6

STB_IO_LDO

RW

0x0

Value for STB_IO_LDO overwrite interface

5

IO_LDO_EN

RW

0x0

Value for IO_LDO overwrite interface

4

RSVD

R

0x0

 Reserved bits

3

DIG_LDO_EN

RW

0x0

Value for CORE_LDO overwrite interface

2

HF_OSC_EN

RW

0x0

Value for HF_OSC overwrite interface

1

SYS_LDO_EN

RW

0x0

Value for SYS_LDO overwrite interface

0

DCDC_EN

RW

0x0

Value for DC-DC overwrite interface

PMU_INTF_OVR_VAL_0

  • Name: PMU_INTF_OVR_VAL_0 Register
  • Description: PMU_INTF_OVR_VAL_0 Register
  • Base Address: 0x4000A800
  • Offset: 0xC4
  • Reset Value: 0x00003F00
Table 141 PMU_INTF_OVR_VAL_0 Register
Bits Field Name RW Reset Description

31:14

RSVD

R

0x0

 Reserved bits

13:8

AVS_CTL_REF

RW

0x3F

Value for AVS_CTL_REF overwrite interface

7

RNG_OSC_CLK_EN

RW

0x0

Value for RNG_OSC_CLK overwrite interface

6

STB_IO_LDO

RW

0x0

Value for STB_IO_LDO overwrite interface

5

IO_LDO_EN

RW

0x0

Value for IO_LDO overwrite interface

4

RSVD

R

0x0

 Reserved bit

3

DIG_LDO_EN

RW

0x0

Value for CORE_LDO overwrite interface

2

HF_OSC_EN

RW

0x0

Value for HF_OSC overwrite interface

1

SYS_LDO_EN

RW

0x0

Value for SYS_LDO overwrite interface

0

DCDC_EN

RW

0x0

Value for DC-DC overwrite interface

PMU_DVS_CFG_0

  • Name: PMU_DVS_CFG_0 Register
  • Description: PMU_DVS_CFG_0 Register
  • Base Address: 0x4000A800
  • Offset: 0xC8
  • Reset Value: 0x00000088
Table 142 PMU_DVS_CFG_0 Register
Bits Field Name RW Reset Description

31:8

RSVD

R

0x0

 Reserved bits

7:0

DVS_LPD_REG2

RW

0x88

[7]: 0x0: low BOD hysteresis; 0x1: high BOD hysteresis

[6:5]: not used

[4]: Select BOD hysteresis mode. 0x0: HW mode; 0x1: SW mode

[3:0]: BOD trimming value

MPX_CFG

  • Name: MPX_CFG Register
  • Description: MPX_CFG Register
  • Base Address: 0x4000A800
  • Offset: 0xD4
  • Reset Value: 0x00000000
Table 143 MPX_CFG Register
Bits Field Name RW Reset Description

31:8

RSVD

R

0x0

 Reserved bits

7:0

MPX_REG1

RW

0x0

[7] When rg_efuse_mpx_sel = 1, select the eFuse power from MPX pad. When rg_efuse_mpx_sel = 0, do not use eFuse LDO; instead, use MPX as the analog test pad.

[6] rg_en_mpx_dig

[5:3] rg_efuse_mpx_sel

[2] rg_en_bypass

[1:0] NC

PMU_INTF_OVR_RD0

  • Name: PMU_INTF_OVR_RD0 Register
  • Description: PMU_INTF_OVR_RD0 Register
  • Base Address: 0x4000A800
  • Offset: 0xE0
  • Reset Value: 0x00003FAF
Table 144 PMU_INTF_OVR_RD0 Register
Bits Field Name RW Reset Description

31:14

RSVD

R

0x0

 Reserved bits

13:8

AVS_CTL_REF

R

0x3F

Current AVS_CTL_REF value

When PMU_ INTF_OVR_EN_0[8] = 1, the value equals PMU_ INTF_OVR_EN_0[13:8]; when PMU_ INTF_OVR_EN_0[8] = 0, the value equals avs_ctl value.

7

RNG_OSC_CLK_EN

R

0x1

Current RNG_OSC_CLK_EN value

6

STB_IO_LDO

R

0x0

Current STB_IO_LDO value

5

IO_LDO_EN

R

0x1

Current IO_LDO value

4

RSVD

R

0x0

 Reserved bit

3

DIG_LDO_EN

R

0x1

Current CORE_LDO value

2

HF_OSC_EN

R

0x1

Current HF_OSC_EN value

1

SYS_LDO_EN

R

0x1

Current SYS_LDO value

0

DCDC_EN

R

0x1

Current DC-DC value

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