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文档中心 > GR533x Datasheet/ System/ Registers/ Cache Copy URL

Cache

CACHE_REGS

CTRL0

  • Name: CTRL0 Register
  • Description: CTRL0 Register
  • Base Address: 0x4000D000
  • Offset: 0x0
  • Reset Value: 0x00000013
Table 158 CTRL0 Register
Bits Field Name RW Reset Description
31:12 RSVD R 0x0 Reserved bits
11 DIRECT_MAP_EN RW 0x0

Enable direct map.

Value:

  • 0x0: Enable 4-way associative map.
  • 0x1: Enable direct map (no effect for sequential access).
10 CLK_FORCE_EN_3 RW 0x0

Cache_FSM and cache memory clock gating

Value:

  • 0x0: Forcibly disable gating.
  • 0x1: Enable gating dynamically.
9 CLK_FORCE_EN_2 RW 0x0

APB clock gating control

Value:

  • 0x0: Forcibly disable gating.
  • 0x1: Enable gating dynamically.
8 CLK_FORCE_EN_1 RW 0x0

Cache CLK_96 gating control

Value:

  • 0x0: Forcibly disable gating.
  • 0x1: Enable gating dynamically.
7 CLK_FORCE_EN_0 RW 0x0

XQSPI and cache HCLK gating control

Value:

  • 0x0: Forcibly disable gating.
  • 0x1: Enable gating dynamically.
6 BUF_DIS RW 0x0

Disable cache buffer preloading.

Value:

  • 0x0: Enable cache preloading.
  • 0x1: Disable cache preloading.
5 DIS_SEQ RW 0x0

Disable sequential cache access.

Value:

  • 0x0: Enable cache sequential access.
  • 0x1: Disable cache sequential access.
4 HITMISS RW 0x1

Clear hit/miss counters.

Value:

  • 0x0: hit and miss counters in normal mode
  • 0x1: hit and miss counters in clear mode (default)
3 FIFO RW 0x0

Clear LFU FIFO.

Value:

  • 0x0: FIFO in normal mode (default)
  • 0x1: FIFO in clear mode
2 RSVD R 0x0 Reserved bits
1 FLUSH RW 0x1

Enable tag memory flushing.

Out of resetting tag memory will get flushed unless tag memory retention is enabled (tag_ret signal lives in CPU register space).

Value:

  • 0x0: Tag memory flushing is disabled.
  • 0x1: Tag memory flushing is enabled.
0 DIS RW 0x1

Disable cache.

Value:

  • 0x0: Enable cache.
  • 0x1: Disable cache disabled (default).

HIT_COUNT

  • Name: HIT_COUNT Register
  • Description: HIT_COUNT Register
  • Base Address: 0x4000D000
  • Offset: 0x8
  • Reset Value: 0x00000000
Table 159 HIT_COUNT Register
Bits Field Name RW Reset Description

31:0

HITCOUNT

R

0x0

Read cache hit count (if bit[4] of CTRL0 is 0).

MISS_COUNT

  • Name: MISS_COUNT Register
  • Description: MISS_COUNT Register
  • Base Address: 0x4000D000
  • Offset: 0xC
  • Reset Value: 0x00000000
Table 160 MISS_COUNT Register
Bits Field Name RW Reset Description

31:0

MISSCOUNT

R

0x0

Read cache miss count (if bit[4] of CTRL0 is 0).

STAT

  • Name: STAT Register
  • Description: STAT Register
  • Base Address: 0x4000D000
  • Offset: 0x10
  • Reset Value: 0x00000000
Table 161 STAT Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

 Reserved bits

0

STAT

R

0x0

Value:

  • 0x0: tag flushing not busy

  • 0x1: tag flushing busy

QSPI_REGS

TX_DATA

  • Name: TX_DATA Register
  • Description: TX_DATA Register
  • Base Address: 0x4000D400
  • Offset: 0x0
  • Reset Value: 0x00000000
Table 162 TX_DATA Register
Bits Field Name RW Reset Description

31:0

TX

W

0x0

Serial transmit data register

No packing of transmit data is attempted. That is, the number of bits transmitted per FIFO element is determined by the “bitsize” value in the Control Register (e.g. bitsize = 010 means only 12 bits are used). In addition, the “msb1st” value in the Control Register determines whether the least-significant bits or the most-significant bits of the FIFO element are used.

RX_DATA

  • Name: RX_DATA Register
  • Description: RX_DATA Register
  • Base Address: 0x4000D400
  • Offset: 0x4
  • Reset Value: 0x00000000
Table 163 RX_DATA Register
Bits Field Name RW Reset Description

31:0

RX

R

0x0

Serial receive data register

No packing of receive data is attempted. That is, the number of bits stored per FIFO element is determined by the “bitsize” value in the Control Register (e.g. bitsize = 011 means only 16 bits are used).

CTRL

  • Name: CTRL Register
  • Description: CTRL Register
  • Base Address: 0x4000D400
  • Offset: 0xC
  • Reset Value: 0x00000021
Table 164 CTRL Register
Bits Field Name RW Reset Description

31:16

RSVD

R

0x0

Reserved bits

15:14

TXWMARK

RW

0x0

Value:

  • 0x0: QSPI_FIFO_DEPTH/8

  • 0x1: QSPI_FIFO_DEPTH/4

  • 0x2: QSPI_FIFO_DEPTH/2

  • 0x3: QSPI_FIFO_DEPTH/2 + QSPI_FIFO_DEPTH/4

13:12

RXWMARK

RW

0x0

Value:

  • 0x0: QSPI_FIFO_DEPTH/8

  • 0x1: QSPI_FIFO_DEPTH/4

  • 0x2: QSPI_FIFO_DEPTH/2

  • 0x3: QSPI_FIFO_DEPTH/2 + QSPI_FIFO_DEPTH/4

11

MWAITEN

RW

0x0

Value:

  • 0x0: Disable delay (full speed).

  • 0x1: Enable delay.

10

DMA

RW

0x0

Not used

Value:

  • 0x0: Disable DMA mode.

  • 0x1: Enable DMA mode.

9:6

RSVD

R

0x0

Reserved bits

5

MASTER

R

0x1

qspi_master flag

4

CPOL

RW

0x0

Value:

  • 0x0: SPI clock rests low.

  • 0x1: SPI clock rests high.

3

CPHA

RW

0x0

Value:

  • 0x0: First bit(s) of sdataOut occur as SS is asserted.

  • 0x1: sdataOut occurs on first SPI clock edge after SS

2

MSB1ST

RW

0x0

MSB/LSB

  • 0x1: MSB first

  • 0x0: LSB first

1

RSVD

R

0x0

Reserved bits

0

CONTXFER

RW

0x1

Continuous Transfer bit. This is relevant for Master operation only.

Note that this setting also affects the timing of the master output enable signal, sdataOutEnMN.

Value:

  • 0x0: ssOut goes inactive between successive transfers.

  • 0x1: ssOut stays active until the TX FIFO is empty AND the contXferExtend bit (in the Auxiliary Control Register) is low.

AUX_CTRL

  • Name: AUX_CTRL Register
  • Description: AUX_CTRL Register
  • Base Address: 0x4000D400
  • Offset: 0x10
  • Reset Value: 0x00000070
Table 165 AUX_CTRL Register
Bits Field Name RW Reset Description

31:8

RSVD

R

0x0

Reserved bits

7

CONTXFERX

RW

0x0

Continuous Transfer Extend Bit. This is relevant for Master operation only. Further, this bit has no effect if the contXfer bit is 0. This register bit is synchronized to the SCLK domain for use there. Note that this setting also affects the timing of the master output enable signal, sdataOutEnMN.

Value:

  • 0x0: Set to 0 to have ssOut[x] become inactive when the TX FIFO is empty.

  • 0x1: Set to 1 to have ssOut[x] remain active even when the TX FIFO is empty.

6:4

BITSIZE

RW

0x7

Value:

  • 0x0: 4-bit serial mode

  • 0x1: 8-bit serial mode

  • 0x2: 12-bit serial mode

  • 0x3: 16-bit serial mode

  • 0x4: 20-bit serial mode

  • 0x5: 24-bit serial mode

  • 0x6: 28-bit serial mode

  • 0x7: 32-bit serial mode

3

INHIBITDIN

RW

0x0

Set to 1 to inhibit the SPI serializers from writing to the Read Data FIFO.

2

INHIBITDOUT

RW

0x0

Set to 1 to inhibit the SPI serializers from reading the Transmit FIFO.

Note that this is intended to be used as a Slave mode configuration. In many cases, a Slave simply receives data from a Master; in these cases, setting this bit will allow the Slave to receive data without causing a TX FIFO underflow condition.

1:0

QMODE

RW

0x0

Value:

  • 0x0: normal SPI

  • 0x1: reserved

  • 0x2: dual SPI

  • 0x3: quad SPI

STAT

  • Name: STAT Register
  • Description: STAT Register
  • Base Address: 0x4000D400
  • Offset: 0x14
  • Reset Value: 0x0000002C
Table 166 STAT Register
Bits Field Name RW Reset Description

31:8

RSVD

R

0x0

Reserved bits

7

RXFULL

R

0x0

Value:

  • 0x0: RX FIFO is not full.

  • 0x1: RX FIFO is full.

6

RXWMARK

R

0x0

Value:

  • 0x0: The received data is less than the watermark.

  • 0x1: The received data is more than or equal to the watermark.

5

RXEMPTY

R

0x1

Value:

  • 0x0: RX FIFO is not empty.

  • 0x1: RX FIFO is empty.

4

TXFULL

R

0x0

Value:

  • 0x0: TX FIFO is not full.

  • 0x1: TX FIFO is full.

3

TXWMARK

R

0x1

Value:

  • 0x0: The data in TX FIFO is more than the watermark.

  • 0x1: The data in TX FIFO is less than or equal to the watermark.

2

TXEMPTY

R

0x1

Value:

  • 0x0: TX FIFO is not empty.

  • 0x1: TX FIFO is empty.

1

RSVD

R

0x0

Reserved bits

0

XFERIP

R

0x0

Transfer is in progress (ssOut/ssIn is active).

Value:

  • 0x0: CS is inactive.

  • 0x1: CS is active.

SLAVE_SEL

  • Name: SLAVE_SEL Register
  • Description: SLAVE_SEL Register
  • Base Address: 0x4000D400
  • Offset: 0x18
  • Reset Value: 0x00000000
Table 167 SLAVE_SEL Register
Bits Field Name RW Reset Description

31:4

RSVD

R

0x0

Reserved bits

3

OUT3

RW

0x0

Value:

  • 0x0: Do not select slave 1 for TX/RX.

  • 0x1: Select Slave 1 for TX/RX.

Note:

Only bit0 is used.

2

OUT2

RW

0x0

Value:

  • 0x0: Do not select slave 1 for TX/RX.

  • 0x1: Select Slave 1 for TX/RX.

Note:

Only bit0 is used.

1

OUT1

RW

0x0

Value:

  • 0x0: Do not select slave 1 for TX/RX.

  • 0x1: Select Slave 1 for TX/RX.

Note:

Only bit0 is used.

0

OUT0

RW

0x0

Value:

  • 0x0: Do not select slave 1 for TX/RX.

  • 0x1: Select Slave 1 for TX/RX.

Note:

Only bit0 is used.

SLAVE_SEL_POL

  • Name: SLAVE_SEL_POL Register
  • Description: SLAVE_SEL_POL Register
  • Base Address: 0x4000D400
  • Offset: 0x1C
  • Reset Value: 0x00000000
Table 168 SLAVE_SEL_POL Register
Bits Field Name RW Reset Description

31:4

RSVD

R

0x0

Reserved bits

3

POL3

RW

0x0

Value:

  • 0x0: CS is an active low signal.

  • 0x1: CS is an active high signal.

Note:

Only bit0 is used.

2

POL2

RW

0x0

Value:

  • 0x0: CS is an active low signal.

  • 0x1: CS is an active high signal.

Note:

Only bit0 is used.

1

POL1

RW

0x0

Value:

  • 0x0: CS is an active low signal.

  • 0x1: CS is an active high signal.

Note:

Only bit0 is used.

0

POL0

RW

0x0

Value:

  • 0x0: CS is an active low signal.

  • 0x1: CS is an active high signal.

Note:

Only bit0 is used.

INTEN

  • Name: INTEN Register
  • Description: INTEN Register
  • Base Address: 0x4000D400
  • Offset: 0x20
  • Reset Value: 0x00000000
Table 169 INTEN Register
Bits Field Name RW Reset Description

31:7

RSVD

R

0x0

Reserved bits

6:0

INT_EN

RW

0x0

[0] TX FIFO empty interrupt

[1] TX FIFO watermark interrupt

[2] RX FIFO watermark interrupt

[3] RX FIFO full interrupt

[4] ro_xferip from high to low

[5] no use

[6] no use

Value:

  • 0x0: Disable

  • 0x1: Enable

INTSTAT

  • Name: INTSTAT Register
  • Description: INTSTAT Register
  • Base Address: 0x4000D400
  • Offset: 0x24
  • Reset Value: 0x00000000
Table 170 INTSTAT Register
Bits Field Name RW Reset Description

31:5

RSVD

R

0x0

Reserved bits

4:0

INT_STAT

R

0x0

[0] TX FIFO empty flag interrupt

[1] TX FIFO watermark interrupt

[2] RX FIFO watermark interrupt

[3] RX FIFO full interrupt

[4] CS done interrupt

Value:

  • 0x0: no interrupt

  • 0x1: Interrupt source is active.

INTCLR

  • Name: INTCLR Register
  • Description: INTCLR Register
  • Base Address: 0x4000D400
  • Offset: 0x28
  • Reset Value: 0x00000000
Table 171 INTCLR Register
Bits Field Name RW Reset Description

31:5

RSVD

R

0x0

Reserved bits

4:0

INT_CLR

W

0x0

[0] Clear the TX FIFO empty flag interrupt.

[1] Clear the TX FIFO watermark interrupt.

[2] Clear the RX FIFO watermark interrupt.

[3] Clear the RX FIFO full interrupt.

[4] Clear the CS done interrupt.

Value:

  • 0x0: no effect

  • 0x1: Clear the interrupt,

TX_FIFO_LVL

  • Name: TX_FIFO_LVL Register
  • Description: TX_FIFO_LVL Register
  • Base Address: 0x4000D400
  • Offset: 0x2C
  • Reset Value: 0x00000000
Table 172 TX_FIFO_LVL Register
Bits Field Name RW Reset Description

31:5

RSVD

R

0x0

Reserved bits

4:0

TXFIFOLVL

R

0x0

Read the transmit FIFO current level (0–16).

RX_FIFO_LVL

  • Name: RX_FIFO_LVL Register
  • Description: RX_FIFO_LVL Register
  • Base Address: 0x4000D400
  • Offset: 0x30
  • Reset Value: 0x00000000
Table 173 RX_FIFO_LVL Register
Bits Field Name RW Reset Description

31:5

RSVD

R

0x0

Reserved bits

4:0

RXFIFOLVL

R

0x0

Read the transmit FIFO current level (0–16).

MSTR_IT_DELAY

  • Name: MSTR_IT_DELAY Register
  • Description: MSTR_IT_DELAY Register
  • Base Address: 0x4000D400
  • Offset: 0x38
  • Reset Value: 0x00000000
Table 174 MSTR_IT_DELAY Register
Bits Field Name RW Reset Description

31:8

RSVD

R

0x0

Reserved bits

7:0

MWAIT

RW

0x0

If master (Control Register) is 1, this register sets the inter-transfer delay for the master serializer. The delay is (mwait + 1) SCLK cycles.

SPIEN

  • Name: SPIEN Register
  • Description: SPIEN Register
  • Base Address: 0x4000D400
  • Offset: 0x3C
  • Reset Value: 0x00000000
Table 175 SPIEN Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

EN

RW

0x0

Enable SPI.

Value:

  • 0x0: Disable SPI TX and RX; reset RX and TX FIFOs on the transition from 1 to 0 of this bit. Although SPI can be disabled at any time, it is recommended to disable SPI when FIFOs are empty. After writing 0 to the enable bit, read the enable bit back; only after the enable bit is read to be 0, should any further register configurations be performed.

  • 0x1: Enable SPI TX and RX.

RX_DATA0_31

  • Name: RX_DATA0_31 Register
  • Description: RX_DATA0_31 Register
  • Base Address: 0x4000D400
  • Offset: 0x48
  • Reset Value: 0x00000000
Table 176 RX_DATA0_31 Register
Bits Field Name RW Reset Description

31:0

RX_DATA0

R

0x0

32-bit LSB word in RX 128-bit read mode, rx_data[31:0]

RX_DATA32_63

  • Name: RX_DATA32_63 Register
  • Description: RX_DATA32_63 Register
  • Base Address: 0x4000D400
  • Offset: 0x4C
  • Reset Value: 0x00000000
Table 177 RX_DATA32_63 Register
Bits Field Name RW Reset Description

31:0

RX_DATA1

R

0x0

32-bit 2nd LSB word in RX 128-bit read mode, rx_data[63:32]

RX_DATA64_95

  • Name: RX_DATA64_95 Register
  • Description: RX_DATA64_95 Register
  • Base Address: 0x4000D400
  • Offset: 0x50
  • Reset Value: 0x00000000
Table 178 RX_DATA64_95 Register
Bits Field Name RW Reset Description

31:0

RX_DATA2

R

0x0

32-bit 3rd LSB word in RX 128-bit read mode, rx_data[95:64]

RX_DATA96_127

  • Name: RX_DATA96_127 Register
  • Description: RX_DATA96_127 Register
  • Base Address: 0x4000D400
  • Offset: 0x54
  • Reset Value: 0x00000000
Table 179 RX_DATA96_127 Register
Bits Field Name RW Reset Description

31:0

RX_DATA3

R

0x0

32-bit 4th LSB word in RX 128-bit read mode, rx_data[127:96]

FLASH_WRITE

  • Name: FLASH_WRITE Register
  • Description: FLASH_WRITE Register
  • Base Address: 0x4000D400
  • Offset: 0x5C
  • Reset Value: 0x00000000
Table 180 FLASH_WRITE Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

FLASH_WRITE

RW

0x0

Value:

  • 0x0: 128-bit mode

  • 0x1: 32-bit mode (used for Flash programming/write operation)

CS_IDLE_UNVLD_EN

  • Name: CS_IDLE_UNVLD_EN Register
  • Description: CS_IDLE_UNVLD_EN Register
  • Base Address: 0x4000D400
  • Offset: 0x78
  • Reset Value: 0x00000001
Table 181 CS_IDLE_UNVLD_EN Register
Bits Field Name RW Reset Description

31:3

RSVD

R

0x0

Reserved bits

2

KEY_PULSE_DIS

RW

0x0

When CPU reads Flash alias address and Flash address, access to Flash alias address will flush XQSPI FIFO, thus resulting in low performance.

Value:

  • 0x0: Enable key_pulse to interrupt rd_data state.

  • 0x1: Disable key_pulse to interrupt rd_data state.

1

1ST_PRETETCH_DIS

RW

0x0

When XIP_EN_REQ is set, XQSPI will prefetch 256 bytes of data from Flash. Clear this bit to disable this function.

Value:

  • 0x0: Enable 1st prefecth function.

  • 0x1: Disable 1st prefetch function.

0

CS_IDLE_UNVLD_EN

RW

0x1

Value:

  • 0x0: CS keeps valid when the device is not reading data.

  • 0x1: CS keeps invalid when the device is not reading data.

XIP_REGS

CTRL0

  • Name: CTRL0 Register
  • Description: CTRL0 Register
  • Base Address: 0x4000DC00
  • Offset: 0x0
  • Reset Value: 0x00000003
Table 182 CTRL0 Register
Bits Field Name RW Reset Description

31:8

RSVD

R

0x0

Reserved bits

7:0

CMD

RW

0x3

XIP configuration read command

Value:

  • 0x03: read

  • 0x0B: fast read

  • 0x3B: fast dual out read

  • 0x6B: fast quad out read

  • 0xBB: fast dual I/O read

  • 0xEB: fast quad I/O read

  • All others: reserved

CTRL1

  • Name: CTRL1 Register
  • Description: CTRL1 Register
  • Base Address: 0x4000DC00
  • Offset: 0x4
  • Reset Value: 0x00000108
Table 183 CTRL1 Register
Bits Field Name RW Reset Description

31:9

RSVD

R

0x0

Reserved bits

8

LE32

RW

0x1

XIP configuration 128-bit little endian arrangement of read data

Value:

  • 0x0: The read data is in big endian mode.

  • 0x1: The read data is in 128-bit little endian mode.

7

ADDR4

RW

0x0

XIP configuration 4-byte address mode

Value:

  • 0x0: XIP issues 3-byte address

  • 0x1: XIP issues 4-byte SPI address

6

CPOL

RW

0x0

XIP configuration CPOL mode

Value:

  • 0x0: CPOL mode 0

  • 0x1: CPOL mode 1

5

CPHA

RW

0x0

XIP configuration CPHA mode

Value:

  • 0x0: CPHA mode 0

  • 0x1: CPHA mode 1

4:1

SS

RW

0x4

XIP configuration slave select

Value:

  • 0x1: slave select 0

  • 0x2: slave select 1

  • 0x4: slave select 2

  • 0x8: slave select 3

  • All others: reserved

0

HPEN

RW

0x0

XIP configuration high performance mode

Value:

  • 0x0: Disable HP mode.

  • 0x1: Enable HP mode.

CTRL2

  • Name: CTRL2 Register
  • Description: CTRL2 Register
  • Base Address: 0x4000DC00
  • Offset: 0x8
  • Reset Value: 0x000000A3
Table 184 CTRL2 Register
Bits Field Name RW Reset Description

31:14

RSVD

R

0x0

Reserved bits

13:12

ENDDUMMY

RW

0x0

Configure the number of dummy cycles necessary to terminate high performance mode. This is used by the core when exiting XIP mode after performing high-performance transfers to ensure that FLASH device is not still in HP mode. For Quad mode, this value is multiplied by 2 to get the actual number of dummy cycles.

11:8

DUMMYCYCLES

RW

0x0

Used to configure the number of dummy cycles used by the core for Fast Read, Fast Read Dual Output, and Fast Read Quad Output.

Fast Read Dual I/O: 4 x value + 4

Fast Read Quad I/O: 2 x value + 2

Fast Read Quad Output: 8 x value

7:0

HPMODE

RW

0xA3

XIP mode command byte. This byte is transferred from core to QSPI Flash memory. It is the value specified by different QSPI Flash memory vendors to enter into its status register to activate HP mode in dual I/O and Quad I/O accesses.

CTRL3

  • Name: CTRL3 Register
  • Description: CTRL3 Register
  • Base Address: 0x4000DC00
  • Offset: 0xC
  • Reset Value: 0x00000000
Table 185 CTRL3 Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

XIP_EN_REQ

RW

0x0

XIP enable request

Value:

  • 0x0: Disable XIP mode.

  • 0x1: Enable XIP mode.

When it is set to 1’b1, do not access QSPI address space. Wait until XIP_EN_OUT is 1’b1. When it is set to 1’b0, do not access QSPI address space. Wait until XIP_EN_OUT is 1’b0.

STAT

  • Name: STAT Register
  • Description: STAT Register
  • Base Address: 0x4000DC00
  • Offset: 0x10
  • Reset Value: 0x00000000
Table 186 STAT Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

XIP_EN_OUT

R

0x0

XIP enable status

Value:

  • 0x0: XIP mode is disabled.

  • 0x1: XIP mode is enabled.

INTEN

  • Name: INTEN Register
  • Description: INTEN Register
  • Base Address: 0x4000DC00
  • Offset: 0x14
  • Reset Value: 0x00000000
Table 187 INTEN Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

XIP_INT_EN

R

0x0

Enable interrupt.

Value:

  • 0x0: Disable interrupt.

  • 0x1: Enable interrupt.

INTSTAT

  • Name: INTSTAT Register
  • Description: INTSTAT Register
  • Base Address: 0x4000DC00
  • Offset: 0x18
  • Reset Value: 0x00000000
Table 188 INTSTAT Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

XIP_INT_STAT

R

0x0

Interrupt status

Value:

  • 0x0: No interrupt occurred.

  • 0x1: An interrupt occurred.

INTREQ

  • Name: INTREQ Register
  • Description: INTREQ Register
  • Base Address: 0x4000DC00
  • Offset: 0x1C
  • Reset Value: 0x00000000
Table 189 INTREQ Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

XIP_INT_REQ

R

0x0

Output interrupt.

Value:

  • 0x0: No interrupt occurred or interrupt is disabled.

  • 0x1: An interrupt occurred and interrupt is enabled.

INTSET

  • Name: INTSET Register
  • Description: INTSET Register
  • Base Address: 0x4000DC00
  • Offset: 0x20
  • Reset Value: 0x00000000
Table 190 INTSET Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

XIP_INT_SET

W

0x0

Interrupt enable set

Value:

  • 0x0: no action

  • 0x1: Set the related bit to 1.

INTCLR

  • Name: INTCLR Register
  • Description: INTCLR Register
  • Base Address: 0x4000DC00
  • Offset: 0x24
  • Reset Value: 0x00000000
Table 191 INTCLR Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

XIP_INT_CLR

W

0x0

Interrupt enable clear

Value:

  • 0x0: no action

  • 0x1: Clear the related bit to 0.

SOFT_RST

  • Name: SOFT_RST Register
  • Description: SOFT_RST Register
  • Base Address: 0x4000DC00
  • Offset: 0x28
  • Reset Value: 0x00000001
Table 192 SOFT_RST Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

XIP_SOFT_RST

RW

0x0

Soft reset IP by writing 1’b0, and then internal logic generates active low reset for one HCLK cycle.

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