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GR533x Datasheet

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文档中心 > GR533x Datasheet/ System/ Registers/ Always-on Power Control Copy URL

Always-on Power Control

A_TIMING_CTRL0

Name: A_TIMING_CTRL0 Register
Description: A_TIMING_CTRL0 Register
Base Address: 0x4000A400
Offset: 0x0
Reset Value: 0x0009001E

Table 100 A_TIMING_CTRL0 Register
Bits	Field Name	RW	Reset	Description
31:20	RSVD	R	0x0	Reserved bits
19:16	DIG_LDO	RW	0x9	CORE_LDO timing required for power-on
15:5	RSVD	R	0x0	Reserved bits
4:0	DCDC	RW	0x1E	DC-DC timing required for power-on

A_TIMING_CTRL1

Name: A_TIMING_CTRL1 Register
Description: A_TIMING_CTRL1 Register
Base Address: 0x4000A400
Offset: 0x4
Reset Value: 0x00070009

Table 101 A_TIMING_CTRL1 Register
Bits	Field Name	RW	Reset	Description
31:20	RSVD	R	0x0	Reserved bits
19:16	HF_OSC	RW	0x7	HF_OSC timing required for stability
15:4	RSVD	R	0x0	Reserved bits
3:0	FAST_LDO	RW	0x9	FAST_LDO timing required for power-on

A_TIMING_CTRL2

Name: A_TIMING_CTRL2 Register
Description: A_TIMING_CTRL2 Register
Base Address: 0x4000A400
Offset: 0x8
Reset Value: 0x0003003B

Table 102 A_TIMING_CTRL2 Register
Bits	Field Name	RW	Reset	Description
31:21	RSVD	R	0x0	Reserved bits
20:16	PLL	RW	0x3	PLL timing required for stability
15:6	RSVD	R	0x0	Reserved bits
5:0	PLL_LOCK	RW	0x3B	PLL lock timing required for stability

A_TIMING_CTRL3

Name: A_TIMING_CTRL3 Register
Description: A_TIMING_CTRL3 Register
Base Address: 0x4000A400
Offset: 0xC
Reset Value: 0x00F90009

Table 103 A_TIMING_CTRL3 Register
Bits	Field Name	RW	Reset	Description
31:24	RSVD	R	0x0	Reserved bits
23:16	XO	RW	0xF9	XO timing required for stability
15:4	RSVD	R	0x0	Reserved bits
3:0	PWR_SWITCH	RW	0x9	IO LDO or standard IO LDO power switch timing required for stability

A_TIMING_CTRL4

Name: A_TIMING_CTRL4 Register
Description: A_TIMING_CTRL4 Register
Base Address: 0x4000A400
Offset: 0x10
Reset Value: 0x000E0095

Table 104 A_TIMING_CTRL4 Register
Bits	Field Name	RW	Reset	Description
31:20	RSVD	R	0x0	Reserved bits
19:16	RF_TUNE	RW	0xE	RF_TUNE timing required for stability
15:8	RSVD	R	0x0	Reserved bits
7:0	XO_BIAS_SW	RW	0x95	XO bias timing required for stability

A_SLP_CFG

Name: A_SLP_CFG Register
Description: A_SLP_CFG Register
Base Address: 0x4000A400
Offset: 0x20
Reset Value: 0x00070017

Table 105 A_SLP_CFG Register
Bits	Field Name	RW	Reset	Description
31:19	RSVD	R	0x0	Reserved bits
18	TRN_ON_STB_LDO	RW	0x1	Value: 0x0: Keep the current status. 0x1: Turn on the standby IO_LDO power switch in sleep mode.
17	TRN_OFF_PLL	RW	0x1	PLL status in sleep mode Value: 0x0: Keep the current status. 0x1: Turn off
16	TRN_OFF_XO	RW	0x1	XO status in sleep mode Value: 0x0: Keep the current status. 0x1: Turn off
15:5	RSVD	R	0x0	Reserved bits
4	TRN_OFF_FAST_LDO	RW	0x1	FAST_LDO status in sleep mode Value: 0x0: Keep the current status. 0x1: Turn off
3	TRN_OFF_IO_LDO	RW	0x0	IO_LDO status in sleep mode Value: 0x0: Keep the current status. 0x1: Turn off
2	TRN_OFF_HF_OSC	RW	0x1	HF_OSC status in sleep mode Value: 0x0: Keep the current status. 0x1: Turn off
1	TRN_OFF_DIG_LDO	RW	0x1	CORE_LDO status in sleep mode Value: 0x0: Keep the current status. 0x1: Turn off
0	TRN_OFF_DCDC	RW	0x1	DC-DC status in sleep mode Value: 0x0: Keep the current status. 0x1: Turn off

AON_START_CFG

Name: AON_START_CFG Register
Description: AON_START_CFG Register
Base Address: 0x4000A400
Offset: 0x24
Reset Value: 0x00000056

Table 106 AON_START_CFG Register
Bits	Field Name	RW	Reset	Description
31:7	RSVD	R	0x0	Reserved bits
6	PLL_EN_PWR	RW	0x1	1: Enable PLL after DC-DC gets ready.
5	RSVD	R	0x0	Reserved bit
4	XO_EN_PWR	RW	0x1	1: Enable XO after DC-DC gets ready.
3	RSVD	R	0x0	Reserved bit
2:1	POWER_MODE	RW	0x3	Power mode: Value: 0x0: Start with DC-DC only. 0x1: Boot with SYS_LDO only. 0x2: Start DC-DC and SYS_LDO at the same time, and the hardware closes SYS_LDO after completion. 0x3: Start DC-DC and SYS_LDO at the same time, both of which remain on after completion.
0	RSVD	R	0x0	Reserved bit

DPAD_LE_CTRL

Name: DPAD_LE_CTRL Register
Description: DPAD_LE_CTRL Register
Base Address: 0x4000A400
Offset: 0x28
Reset Value: 0x00040100

Table 107 DPAD_LE_CTRL Register
Bits	Field Name	RW	Reset	Description
31:19	RSVD	R	0x0	Reserved bits
18	WAKEUP	RW	0x1	Set HW controlled dpad_le value after waking up.
17	RSVD	R	0x0	Reserved bit
16	SLEEP	RW	0x0	Set HW controlled dpad_le value during sleep.
15:11	RSVD	R	0x0	Reserved bits
10	BUSY	R	0x0	DPAD_LE_CTRL is applying a value. Do not apply a value again.
9	RSVD	R	0x0	Reserved bit
8	READ	R	0x1	The current DPAD Latch value
7:3	RSVD	R	0x0	Reserved bits
2	APPLY_WR	W	0x0	Write 1 to apply the value of WR to control signal.
1	RSVD	R	0x0	Reserved bit
0	WR	RW	0x0	Enable DPAD Latch. Value: 0x0: Latch the pad configurations. 0x1: The DPAD latch is transparent.

AON_SLP_CTRL

Name: AON_SLP_CTRL Register
Description: AON_SLP_CTRL Register
Base Address: 0x4000A400
Offset: 0x3C
Reset Value: 0x00000000

Table 108 AON_SLP_CTRL Register
Bits	Field Name	RW	Reset	Description
31:9	RSVD	R	0x0	Reserved bits
8	PRO	R	0x0	The power controller is processing a deep-sleep request.
7:1	RSVD	R	0x0	Reserved bits
0	REQ	W	0x0	Write 1 to send a sleep request.

XO_PLL_SET

Name: XO_PLL_SET Register
Description: XO_PLL_SET Register
Base Address: 0x4000A400
Offset: 0x40
Reset Value: 0x00000000

Table 109 XO_PLL_SET Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	HF_OSC_SET	W	0x0	Write 1 to enable HFOSC. This operation will turn DC-DC on if it is not.
1	XO_SET	W	0x0	Write 1 to enable HFXO. This operation will turn DC-DC on if it is not.
0	PLL_SET	W	0x0	Write 1 to enable CPLL. This operation will turn DC-DC on if it is not.

XO_PLL_CLR

Name: XO_PLL_CLR Register
Description: XO_PLL_CLR Register
Base Address: 0x4000A400
Offset: 0x44
Reset Value: 0x00000000

Table 110 XO_PLL_CLR Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	HF_OSC_CLR	W	0x0	Write 1 to disable HFOSC.
1	XO_CLR	W	0x0	Write 1 to disable HFXO.
0	PLL_CLR	W	0x0	Write 1 to disable CPLL.

XO_PLL_STAT

Name: XO_PLL_STAT Register
Description: XO_PLL_STAT Register
Base Address: 0x4000A400
Offset: 0x48
Reset Value: 0x00000007

Table 111 XO_PLL_STAT Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	HF_STAT	R	0x1	HF_OSC stable state
1	XO_STAT	R	0x1	XO stable state
0	PLL_STAT	R	0x1	PLL stable state

PWR_SET

Name: PWR_SET Register
Description: PWR_SET Register
Base Address: 0x4000A400
Offset: 0x4C
Reset Value: 0x00000000

Table 112 PWR_SET Register
Bits	Field Name	RW	Reset	Description
31:6	RSVD	R	0x0	Reserved bits
5	STB_IO_LDO_SET	W	0x0	Write '1' to enable STB_IO_LDO.
4	IO_LDO_SET	W	0x0	Write '1' to enable IO_LDO.
3	RSVD	R	0x0	Reserved bit
2	FAST_LDO_SET	W	0x0	Fast LDO power request
1	DIG_LDO_SET	W	0x0	CORE_LDO power request
0	DCDC_SET	W	0x0	DC-DC power request

PWR_CLR

Name: PWR_CLR Register
Description: PWR_CLR Register
Base Address: 0x4000A400
Offset: 0x50
Reset Value: 0x00000000

Table 113 PWR_CLR Register
Bits	Field Name	RW	Reset	Description
31:6	RSVD	R	0x0	Reserved bits
5	STD_IO_LDO_CLR	W	0x0	Write '1' to disable STB_IO_LDO.
4	IO_LDO_CLR	W	0x0	Write '1' to disable IO_LDO.
3	RSVD	R	0x0	Reserved bit
2	FAST_LDO_CLR	W	0x0	Disable Fast LDO power.
1	DIG_LDO_CLR	W	0x0	Disable CORE_LDO power.
0	DCDC_CLR	W	0x0	Disable DC-DC power.

PWR_STAT

Name: PWR_STAT Register
Description: PWR_STAT Register
Base Address: 0x4000A400
Offset: 0x54
Reset Value: 0x00000007

Table 114 PWR_STAT Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	FAST_LDO_AVL	R	0x1	Fast LDO power is available. The status is NOT valid if analog interface overriding is used.
1	DIG_LDO_AVL	R	0x1	CORE_LDO power is available. The status is NOT valid if analog interface overriding is used.
0	DCDC_AVL	R	0x1	DC-DC power is available. The status is NOT valid if analog interface overriding is used.

MEM_PWR_SLP0

Name: MEM_PWR_SLP0 Register
Description: MEM_PWR_SLP0 Register
Base Address: 0x4000A400
Offset: 0x80
Reset Value: 0x00000FFF

Table 115 MEM_PWR_SLP0 Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R	0x0	Reserved bits
11:10	SET05	RW	0x3	Memory power states that is loaded in sleep phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
9:8	SET04	RW	0x3	Memory power states that is loaded in sleep phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
7:6	SET03	RW	0x3	Memory power states that is loaded in sleep phase Value: 0x0: OFF 0x1: Reserved 0x2: full power 0x3: retention
5:4	SET02	RW	0x3	Memory power states that is loaded in sleep phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
3:2	SET01	RW	0x3	Memory power states that is loaded in sleep phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
1:0	SET00	RW	0x3	Memory power states that is loaded in sleep phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention

MEM_PWR_SLP1

Name: MEM_PWR_SLP1 Register
Description: MEM_PWR_SLP1 Register
Base Address: 0x4000A400
Offset: 0x84
Reset Value: 0x0000003C

Table 116 MEM_PWR_SLP1 Register
Bits	Field Name	RW	Reset	Description
31:6	RSVD	R	0x0	Reserved bits
5:4	ICACHE_SET	RW	0x3	Cache memory sleep power Memory power states that is loaded in sleep phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
3:2	HTM_DM_SET	RW	0x3	Hopping table DM memory sleep power Memory power states that is loaded in sleep phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
1:0	RSVD	R	0x0	Reserved bits

MEM_PWR_WKUP0

Name: MEM_PWR_WKUP0 Register
Description: MEM_PWR_WKUP0 Register
Base Address: 0x4000A400
Offset: 0x88
Reset Value: 0x00000AAA

Table 117 MEM_PWR_WKUP0 Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R	0x0	Reserved bits
11:10	SET05	RW	0x2	Memory power states that is loaded in wakeup phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
9:8	SET04	RW	0x2	Memory power states that is loaded in wakeup phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
7:6	SET03	RW	0x2	Memory power states that is loaded in wakeup phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
5:4	SET02	RW	0x2	Memory power states that is loaded in wakeup phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
3:2	SET01	RW	0x2	Memory power states that is loaded in wakeup phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
1:0	SET00	RW	0x2	Memory power states that is loaded in wakeup phase Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention

MEM_PWR_WKUP1

Name: MEM_PWR_WKUP1 Register
Description: MEM_PWR_WKUP1 Register
Base Address: 0x4000A400
Offset: 0x8C
Reset Value: 0x00000020

Table 118 MEM_PWR_WKUP1 Register
Bits	Field Name	RW	Reset	Description
31:6	RSVD	R	0x0	Reserved bits
5:4	ICACHE	RW	0x2	Cache memory sleep power Memory power states that is loaded on wakeup Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
3:2	HTM_DM	RW	0x0	Hopping table DM memory sleep power Memory power states that is loaded on wakeup Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
1:0	RSVD	R	0x0	Reserved bits

MEM_PWR_APPLY

Name: MEM_PWR_APPLY Register
Description: MEM_PWR_APPLY Register
Base Address: 0x4000A400
Offset: 0x90
Reset Value: 0x00000000

Table 119 MEM_PWR_APPLY Register
Bits	Field Name	RW	Reset	Description
31:17	RSVD	R	0x0	Reserved bits
16	BUSY	R	0x0	During the bit being 1, writing APPLY would not take any effect.
15:1	RSVD	R	0x0	Reserved bits
0	APPLY	W	0x0	Write 1 to apply the memory settings in MEM_PWR_WKUP manually.

MEM_PWR_STAT0

Name: MEM_PWR_STAT0 Register
Description: MEM_PWR_STAT0 Register
Base Address: 0x4000A400
Offset: 0x98
Reset Value: 0x00000AAA

Table 120 MEM_PWR_STAT0 Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R	0x0	Reserved bits
11:10	SET05	R	0x2	Memory power states. Do NOT read when MEM_PWR_APPLY_BUSY is high. Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
9:8	SET04	R	0x2	Memory power states. Do NOT read when MEM_PWR_APPLY_BUSY is high. Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
7:6	SET03	R	0x2	Memory power states. Do NOT read when MEM_PWR_APPLY_BUSY is high. Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
5:4	SET02	R	0x2	Memory power states. Do NOT read when MEM_PWR_APPLY_BUSY is high. Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
3:2	SET01	R	0x2	Memory power states. Do NOT read when MEM_PWR_APPLY_BUSY is high. Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
1:0	SET00	R	0x2	Memory power states. Do NOT read when MEM_PWR_APPLY_BUSY is high. Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention

MEM_PWR_STAT1

Name: MEM_PWR_STAT1 Register
Description: MEM_PWR_STAT1 Register
Base Address: 0x4000A400
Offset: 0x9C
Reset Value: 0x00000020

Table 121 MEM_PWR_STAT1 Register
Bits	Field Name	RW	Reset	Description
31:6	RSVD	R	0x0	Reserved bits
5:4	ICACHE_SET	R	0x2	Memory power states. Do not read when MEM_PWR_APPLY_BUSY is high. Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
3:2	HTM_DM_SET	R	0x0	Memory power states. Do not read when MEM_PWR_APPLY_BUSY is high. Value: 0x0: OFF 0x1: reserved 0x2: full power 0x3: retention
1:0	RSVD	R	0x0	Reserved bits

MEM_PWR_DBG

Name: MEM_PWR_DBG Register
Description: MEM_PWR_DBG Register
Base Address: 0x4000A400
Offset: 0xBC
Reset Value: 0x00000000

Table 122 MEM_PWR_DBG Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R	0x0	Reserved bits
0	RESET_ON_SRAM	RW	0x0	1: When MCU issues a system-reset request, turn ON all SRAM power. Do not change this register when system-reset is ongoing.

COMM_CORE_PWR_CTRL_SW

Name: COMM_CORE_PWR_CTRL_SW Register
Description: COMM_CORE_PWR_CTRL_SW Register
Base Address: 0x4000A400
Offset: 0xC0
Reset Value: 0x00000002

Table 123 COMM_CORE_PWR_CTRL_SW Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	RST_N	RW	0x0	Comm proc reset active low When this bit is 0, Bluetooth LE is held in reset.
1	ISO_EN	RW	0x1	Enable comm_core power domain isolation. Value: 0x0: NO isolation 0x1: isolated
0	CORE_EN	RW	0x0	Enable comm_core power domain power. Value: 0x0: OFF 0x1: ON

COMM_CORE_PWR_CTRL_HW_CFG

Name: COMM_CORE_PWR_CTRL_HW_CFG Register
Description: COMM_CORE_PWR_CTRL_HW_CFG Register
Base Address: 0x4000A400
Offset: 0xC4
Reset Value: 0x00020200

Table 124 COMM_CORE_PWR_CTRL_HW_CFG Register
Bits	Field Name	RW	Reset	Description
31:19	RSVD	R	0x0	Reserved bits
18	PD_HOLD_EN_RD	R	0x0	Real-time status of PD_HOLD_EN
17	AUTO_EN_RD	R	0x1	Real-time status of AUTO_ON
16	HW_EN_RD	R	0x0	Real-time status of HW_EN
15:12	RSVD	R	0x0	Reserved bits
11	PLL_AUTO_ON	RW	0x0	Waking Bluetooth LE timer up will enable PLL automatically.
10	PD_HOLD_EN	RW	0x0	Wait the Bluetooth LE timer flag and the delay counter before powering off Bluetooth LE.
9	AUTO_EN	RW	0x1	1: If HW sequencer is selected, set 1 to let HW automatically request power-on when a COMM Timer wakeup signal is received. Please allow 6 μs–12 μs for the configuration to be applied.
8	HW_EN	RW	0x0	Enable the hardware sequencer block. Please allow 6 μs–12 μs for the configuration to be applied.
7:1	RSVD	R	0x0	Reserved bits
0	CTRL_SEL	RW	0x0	Value: 0x0: Use the register (`COMM_CORE_PWR_CTRL_SW`) to control comm_core power sequence. 0x1: Use Hardware power sequencer.

COMM_CORE_PWR_CTRL_HW_CTRL

Name: COMM_CORE_PWR_CTRL_HW_CTRL Register
Description: COMM_CORE_PWR_CTRL_HW_CTRL Register
Base Address: 0x4000A400
Offset: 0xC8
Reset Value: 0x00000000

Table 125 COMM_CORE_PWR_CTRL_HW_CTRL Register
Bits	Field Name	RW	Reset	Description
31:9	RSVD	R	0x0	Reserved bits
8	DIS	W	0x0	Write 1 to start comm_core power-off sequence. Writing it to 0 will take no effect.
7:1	RSVD	R	0x0	Reserved bits
0	REQ	W	0x0	Write 1 to start comm_core power-on sequence. Writing it to 0 will take no effect.

COMM_CORE_PWR_CTRL_HW_STAT

Name: COMM_CORE_PWR_CTRL_HW_STAT Register
Description: COMM_CORE_PWR_CTRL_HW_STAT Register
Base Address: 0x4000A400
Offset: 0xCC
Reset Value: 0x00000000

Table 126 COMM_CORE_PWR_CTRL_HW_STAT Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	HW_PD_WAIT	R	0x0	1: Power-off command received, waiting for PD condition
1	HW_PWR	R	0x0	Value: 0x0: OFF state or going to be OFF state 0x1: ON state or going to be ON state
0	BUSY	R	0x0	Value: 0x0: HW power controller is ready to receive a command. 0x1: HW power controller is working.

COMM_CORE_PWR_CTRL_PD_DLY

Name: COMM_CORE_PWR_CTRL_PD_DLY Register
Description: COMM_CORE_PWR_CTRL_PD_DLY Register
Base Address: 0x4000A400
Offset: 0xD0
Reset Value: 0x00000000

Table 127 COMM_CORE_PWR_CTRL_PD_DLY Register
Bits	Field Name	RW	Reset	Description
31:17	RSVD	R	0x0	Reserved bits
16	PD_FLAG	RW	0x0	1: Do not wait for Bluetooth LE timer flag to power off the Bluetooth LE.
15:8	RSVD	R	0x0	Reserved bits
7:0	PD_DLY	RW	0x0	Delay after receiving Bluetooth LE timer flag 0: no delay > 0: N x 4 μs

COMM_CORE_PWR_STAT

Name: COMM_CORE_PWR_STAT Register
Description: COMM_CORE_PWR_STAT Register
Base Address: 0x4000A400
Offset: 0xD4
Reset Value: 0x00000002

Table 128 COMM_CORE_PWR_STAT Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	RST_N_RD	R	0x0	Comm proc reset active low When this bit is 0, Bluetooth LE is held in reset.
1	ISO_EN_RD	R	0x1	Enable comm_core power domain isolation. Value: 0x0: NO isolation 0x1: isolated
0	CORE_EN_RD	R	0x0	Enable comm_core power domain power. Value: 0x0: OFF 0x1: ON

COMM_TIMER_PWR_CTRL

Name: COMM_TIMER_PWR_CTRL Register
Description: COMM_TIMER_PWR_CTRL Register
Base Address: 0x4000A400
Offset: 0xE0
Reset Value: 0x00000002

Table 129 COMM_TIMER_PWR_CTRL Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	RST_N	RW	0x0	Comm timer reset This bit is used to reset the Comm timer after it has been powered on. Value: 0x0: Comm timer reset 0x1: Comm timer reset released
1	ISO_EN	RW	0x1	Enable comm_timer power domain isolation. Value: 0x0: NO isolation 0x1: isolated
0	EN	RW	0x0	Enable comm_timer power domain power. Value: 0x0: OFF 0x1: ON

SOFTWARE_REG_3

Name: SOFTWARE_REG_3 Register
Description: SOFTWARE_REG_3 Register
Base Address: 0x4000A400
Offset: 0xE8
Reset Value: 0x00000000

Table 130 SOFTWARE_REG_3 Register
Bits	Field Name	RW	Reset	Description
31:0	SOFTWARE_REG3	RW	0x0	Software can use this register to save data. It will not be reset by NVIC or in sleep.

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