Always-on RF Control

31:24

RSVD

R

0x0

23:16

RF_MUX_REG2

RW

0x0

[7] if 0 --> 1 MHz clock; if 1 --> 2 MHz

[6] 0: TPP; 1: TPN (if tpc_ena = 0); if tpc_ena = 1 --> dda_out

[5] ADC MUX en (Need to disable original MUX: RF_MUX_REG1[7] = 0)

[4:1] NC

[0] ADCMUX_en

15:8

RSVD

R

0x0

7:0

RF_MUX_REG1

RW

0x0

[7] 1: Enable test MUX; 0: tri-state

[6:4] block selection

[3] 1: TPP; 0: TPN

[2:0] signal selection inside block

31:0

RF_CPLL_REG1

RW

0x38C6A8B0

[30] NC

[29:28] Pre division before CP (00: no division;11: divided by 16); default: div 16

[27:23] CPLL loop filter third capacitor control - 2.4 pF max

[22:18] CPLL loop filter second capacitor control - 4.8 pF max

[17:13] CPLL loop filter first capacitor control – 56 pF max

[12:8] CPLL loop filter resistor control – 160 kohm max

[7:6] Control clock freq. doubler delay, to attain 50% duty cycle.

[5] Select current source. 1 = from bandgap; 0 = from GM bias cell

[4] Select current source. 1 = from bandgap; 0 = from GM bias cell

[3] Enable clock freq. doubler.

[2] Enable CPLL VCO.

[1] 1: cpll_rst_n = 0, reset DPLL; 0: cpll_rst_n follows sequencer.

[0] Select MUX control (0 = CPLL CLK out; 1 = doubler CLK out)

31:0

RF_CPLL_REG2

RW

0x05808492

[31:30] TH

[29:28] TL

[27:26] extra divider after the "m_div", to increase DPLL counting accuracy

[25:18] DPLL ideal count

[17] MUX control to select the source of the KVCO word (0 = DPLL engine; 1 = external word)

[16:12] coarse tuning bits for VCO to set the mid frequency near the locking frequency

[11:9] charge pump code programmability (000-5 μA to 111-40 μA); default: 15 μA

[8:6] CPLL VCO KVCO control; default: 96 MHz/V

[5:0] feedback divider; default: divided by 48

31:0

RF_XO_REG1

RW

0x4F261008

[31:28] comparator reference to disable the chirp noise injection

[27:24] Control the strength of chirp buffers to limit over drive of crystal; LSB must be 1.

[23:20] chirp oscillator KVCO and center frequency control; 1111 = highest frequency and KVCO

[19:17] chirp oscillator ramp control; 111 - slowest; 000- fastest

[16] Double the current of the biasing circuit.

[15] noise injection to be enabled in SU sequence

[14] Negative cap generator to be enabled in SU sequence

[13] Need to transition to high with xo_enable for fast SU.

[12:8] CK_LDO trimming control bits

[7] Use the CK_LDO as a switch (bypass regulation).

[6] Enable internal load for stability.

[5] Double the current of the biasing circuit.

[4:0] XO core current programmability; 32 μA (00001) to 992 μA (11111), unit: 32 μA

31:0

RF_XO_REG2

RW

0x25B40094

[31] rc_cal_ena

[30] rc_cal_reset_b

[29:28] rc_cal_prediv

[27:20] rc_cal_n_ideal_count

[19] rc_cal_override

[18:10] Cload programmability from 50 fF to 26 pF on each side

[9:5] number of Xtal cycles for frequency settling after all SU sequences are done

<11>: 128 μs; <10>: 64 μs; <9>: 32 μs; <8>: 16 μs; <7>: 8 μs; default: 32 μs

[4:0] number of Xtal cycles before disconnecting negative cap

<11>: 128 μs; <10>: 64 μs; <9>: 32 μs; <8>: 16 μs; <7>: 8 μs; default: 160 μs

31:21

RSVD

R

0x0

20:16

CPLL_CRSCDE

R

0x0

PLL frequency value

15:8

RSVD

R

0x0

7:0

RF_ID

R

0x0

RF ID number

31

RSVD

R

0x0

30:22

CAP_LO

RW

0x100

XO capacitance parameter

21:16

BIAS_LO

RW

0x28

XO bias parameter

15

RSVD

R

0x0

14:6

CAP_HI

RW

0x100

XO capacitance parameter

5:0

BIAS_HI

RW

0x28

XO bias parameter

31:24

RSVD

R

0x0

3

RST_N

RW

0x0

Value for rst_n overwrite interface

2

CPLL_EN

RW

0x0

Value for cpll_en overwrite interface

1

TUNE_EN

RW

0x0

Value for tune_en overwrite interface

0

XO_EN

RW

0x0

Value for xo_en overwrite interface

31:24

RSVD

R

0x0

3

RST_N

RW

0x0

Value for rst_n overwrite interface

2

CPLL_EN

RW

0x0

Value for cpll_en overwrite interface

1

TUNE_EN

RW

0x0

Value for tune_en overwrite interface

0

XO_EN

RW

0x0

Value for xo_en overwrite interface

31:24

RSVD

R

0x0

3

RST_N

R

0x0

Current rst_n value. When RF_INTF_OVR_EN_0[3] = 0x1, the value equals RF_INTF_OVR_VAl_0[3]; when RF_INTF_OVR_EN_0[3] = 0x0, the value is controlled by software.

2

CPLL_EN

R

0x0

Current cpll_en value

1

TUNE_EN

R

0x0

Current tune_en value

0

XO_EN

R

0x0

Current xo_en value

31:1

RSVD

R

0x0

0

XO_BIAS_SW

RW

0x0

Value for xo_bias overwrite interface

31:1

RSVD

R

0x0

0

XO_BIAS_SW

RW

0x0

Value for xo_bias overwrite interface

31:1

RSVD

R

0x0

0

XO_BIAS_SW

R

0x0

Value for xo_bias overwrite interface