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无匹配项 共计114个匹配页面
文档中心 > GR533x Datasheet/ System/ Registers/ DDVS Copy URL

DDVS

DDVS_EN

  • Name: DDVS_EN Register
  • Description: DDVS_EN Register
  • Base Address: 0x4000E800
  • Offset: 0x0
  • Reset Value: 0x00000000
Table 238 DDVS_EN Register
Bits Field Name RW Reset Description

31:1

RSVD

R

0x0

Reserved bits

0

DDVS_EN

RW

0x0

Enable DDVS.

Value:

  • 0x0: Disable DDVS (default).

  • 0x1: Enable DDVS.

DDVS_CFG_1

  • Name: DDVS_CFG_1 Register
  • Description: DDVS_CFG_1 Register
  • Base Address: 0x4000E800
  • Offset: 0x4
  • Reset Value: 0x00000000
Table 239 DDVS_CFG_1 Register
Bits Field Name RW Reset Description
31 CONF_DDVS_MODE RW 0x0

DDVS mode

Value:

  • 0x0: DDVS automatic mode (default)
  • 0x1: DDVS manual mode
30:29 CONF_DIV_FACTOR RW 0x0

Ringo frequency division factor

Value:

  • 0x0: 8K (default)
  • 0x1: 4K
  • 0x2: 16K
  • 0x3: reserved
28:25 CONF_RINGO_EN RW 0x0

Enable each ringo.

Value:

  • 0x0: Disable all 4 ringos (default).
  • Others: Enable corresponding ringos.
24 CONF_INT_EN RW 0x0

Enable error interrupt.

Value:

  • 0x0: Disable error interrupt.
  • 0x1: Enable error interrupt.
23 ERR_INT WC 0x0

Error interrupt

Value:

  • 0x0: no error
  • 0x1: error interrupt

Note:

CPU writes 1 to clear, and writing 0 is invalid.
22:17 CONF_VREF_MANUAL RW 0x0

Manual vref

In manual mode, MCU writes this register to set vref.
16 RSVD R 0x0 Reserved bit
15:4 CONF_THRESHOLD_SLOW RW 0x0 Drift slow threshold that changes lock state to re-adjust vref
3:0 RSVD R 0x0 Reserved bits

DDVS_CFG_2

  • Name: DDVS_CFG_2 Register
  • Description: DDVS_CFG_2 Register
  • Base Address: 0x4000E800
  • Offset: 0x8
  • Reset Value: 0x00000000
Table 240 DDVS_CFG_2 Register
Bits Field Name RW Reset Description

31:20

CONF_TARGET_CNT

RW

0x0

Target counter number

19:16

RSVD

R

0x0

Reserved bits

15:4

CONF_THRESHOLD_FAST

RW

0x0

Drift threshold that changes lock state to re-adjust vref

3:0

RSVD

R

0x0

Reserved bits

DDVS_RINGO_CNT_01

  • Name: DDVS_RINGO_CNT_01 Register
  • Description: DDVS_RINGO_CNT_01 Register
  • Base Address: 0x4000E800
  • Offset: 0xC
  • Reset Value: 0x00000000
Table 241 DDVS_RINGO_CNT_01 Register
Bits Field Name RW Reset Description

31:20

RINGO_0_CNT

R

0x0

Ringo 0 counter

19:16

RSVD

R

0x0

Reserved bits

15:4

RINGO_1_CNT

R

0x0

Ringo 1 counter

3:0

RSVD

R

0x0

Reserved bits

DDVS_RINGO_CNT_23

  • Name: DDVS_RINGO_CNT_23 Register
  • Description: DDVS_RINGO_CNT_23 Register
  • Base Address: 0x4000E800
  • Offset: 0x10
  • Reset Value: 0x00000000
Table 242 DDVS_RINGO_CNT_23 Register
Bits Field Name RW Reset Description

31:20

RINGO_2_CNT

R

0x0

Ringo 2 counter

19:16

RSVD

R

0x0

Reserved bits

15:4

RINGO_3_CNT

R

0x0

Ringo 3 counter

3:0

RSVD

R

0x0

Reserved bits

DDVS_FSM

  • Name: DDVS_FSM Register
  • Description: DDVS_FSM Register
  • Base Address: 0x4000E800
  • Offset: 0x14
  • Reset Value: 0x00000000
Table 243 DDVS_FSM Register
Bits Field Name RW Reset Description

31:29

CURR

R

0x0

FSM current state

Value:

  • 0x0: initial state

  • 0x1: vref plus 1

  • 0x2: vref minus 1

  • 0x3: lock

  • 0x4: An error occurs when vref reaches the maximum but still does not meet the system requirement.

  • Others: not used

28:0

RSVD

R

0x0

Reserved bits

DDVS_CLK_CTRL

  • Name: DDVS_CLK_CTRL Register
  • Description: DDVS_CLK_CTRL Register
  • Base Address: 0x4000E800
  • Offset: 0x40
  • Reset Value: 0x00000000
Table 244 DDVS_CLK_CTRL Register
Bits Field Name RW Reset Description

31:10

RSVD

R

0x0

Reserved bits

9:8

CLK_SEL

RW

0x0

Value:

  • 0x0: xo_32MHz

  • 0x1: xo_16MHz

  • 0x2: sys_32MHz

  • 0x3: sys_16MHz

7:1

RSVD

R

0x0

Reserved bits

0

CLK_EN

RW

0x0

Value:

  • 0x0: Disable CLK.

  • 0x1: Enable CLK.

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