Registers
Channel_x Registers
SARx
-
Name: Source Address for Channel x
-
Description: The starting source address is programmed by software before the DMA channel is enabled. While the DMA transfer is in progress, this register is updated to reflect the source address of the current AHB transfer.
Note:You must program the SAR address to be aligned to CTL_LOx.SRC_TR_WIDTH.
-
Base Address: 0x40014000
-
Offset: 0x0 + x*0x58
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:32 |
RSVD |
R |
Reserved bits |
|
31:0 |
CSA |
RW |
0x0 |
Current Source Address of DMA transfer. Updated after each source transfer. The SINC field in the CTL_LOx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true |
DARx
-
Name: Destination Address Register for Channel x
-
Description: The starting destination address is programmed by software before the DMA channel is enabled. While the DMA transfer is in progress, this register is updated to reflect the destination address of the current AHB transfer.
Note:You must program the DAR to be aligned to CTL_LOx.DST_TR_WIDTH.
-
Base Address: 0x40014000
-
Offset: 0x8 + x*0x58
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:32 |
RSVD |
R |
Reserved bits |
|
31:0 |
CDA |
RW |
0x0 |
Current Destination address of DMA transfer. Updated after each destination transfer. The DINC field in the CTL _LOx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true |
CTL_LOx
-
Name: Control Register Low for Channel x
-
Description: This register contains fields that control the DMA transfer.
Note:You need to program this register prior to enabling the channel.
-
Base Address: 0x40014000
-
Offset: 0x18 + x*0x58
-
Reset Value: 0x0000000200304801
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:22 |
RSVD |
R |
Reserved bits Volatile: true |
|
21:20 |
TT_FC |
RW |
0x3 |
Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. Value:
Volatile: true |
19:17 |
RSVD |
R |
Reserved bits Volatile: true |
|
16:14 |
SRC_MSIZE |
RW |
0x1 |
Source burst transaction length. Number of data items, each of width CTL_LOx. SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. Note: This value is not related to the AHB bus master HBURST bus. Value:
Volatile: true |
13:11 |
DST_MSIZE |
RW |
0x1 |
Destination burst transaction length. Number of data items, each of width CTL_LOx. DST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Note: This value is not related to the AHB bus master HBURST bus. Value:
Volatile: true |
10:9 |
SINC |
RW |
0x0 |
Source address increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, set this field to "No change". Value:
Volatile: true |
8:7 |
DINC |
RW |
0x0 |
Destination address increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, set this field to "No Change". Value:
Volatile: true |
6:4 |
SRC_TR_WIDTH |
RW |
0x0 |
Source Transfer Width. Mapped to AHB bus Hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. Value:
Volatile: true |
3:1 |
DST_TR_WIDTH |
RW |
0x0 |
Destination Transfer Width. Mapped to AHB bus Hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. Value:
Volatile: true |
0 |
INT_EN |
RW |
0x1 |
Interrupt Enable Bit. If set, all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw interrupt registers still assert if CTL_LOx.INT_EN = 0. Value:
Volatile: true |
CTL_HIx
-
Name: Control Register High for Channel x
-
Description: This register contains fields that control the DMA transfer.
Note:You need to program this register prior to enabling the channel.
-
Base Address: 0x40014000
-
Offset: 0x1C + x*0x58
-
Reset Value: 0x0000000200304801
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:12 |
RSVD |
R |
Reserved bits Volatile: true |
|
11:0 |
BLOCK_TS |
RW |
0x2 |
Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer; a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTL_LOx. SRC_ TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what the flow controller is. When the source or destination peripheral is assigned as the flow controller, the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true |
CFG_LOx
-
Name: Configuration Register Low for Channel x
-
Description: This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer.
Note:You need to program this register prior to enabling the channel.
- Base Address: 0x40014000
-
Offset: 0x40 + x*0x58
-
Reset Value: 0x0000000400000e00 + (x*0x20)
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:20 |
RESVD |
R |
Reserved bits |
|
19 |
SRC_HS_POL |
RW |
0x0 |
Source handshaking interface polarity. Value:
|
18 |
DST_HS_POL |
RW |
0x0 |
Destination handshaking interface polarity. Value:
|
17:12 |
Rsvd_CFG |
R |
Reserved bits |
|
11 |
HSG_SEL_SRC |
RW |
0x1 |
Selects software or hardware handshaking interface for source. This register selects which of the handshaking interfaces - hardware or software - is active for source requests on this channel. If the source peripheral is memory, this bit is ignored. Value:
|
10 |
HSG_SEL_DEST |
RW |
0x1 |
Selects a software or hardware handshaking interface for destination. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, this bit is ignored. Value:
|
9 |
FIFO_EMPTY |
R |
0x1 |
Channel FIFO status. Indicates if there is data left in the channel FIFO. It can be used in conjunction with CFGx to cleanly disable a channel. Value:
|
8 |
CH_SUSP |
RW |
0x0 |
Channel suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. It can also be used in conjunction with CFGx to cleanly disable a channel without losing any data. Value:
|
7:5 |
CH_PRIOR |
RW |
0x0 |
Channel priority. A priority of 7 is the highest priority and 0 is the lowest. This field must be programmed within the range of 0 to 3. A programmed value beyond this range will cause erroneous behavior. Value:
|
4:0 |
RSVD |
R |
Reserved bits |
CFG_HIx
-
Name: Configuration Register High for Channel x
-
Description: This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer.
Note:You need to program this register prior to enabling the channel.
- Base Address: 0x40014000
-
Offset: 0x40 + x*0x58
-
Reset Value: 0x0000000400000e00 + (x*0x20)
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:15 |
RSVD |
R |
Reserved bits |
|
14:11 |
DEST_PER |
RW |
0x0 |
Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFG_LOx.HSG_SEL_DEST field is 0; otherwise, this field is ignored. The channel can communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. Note: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. |
10:7 |
SRC_PER |
RW |
0x0 |
Source hardware interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_LOx.HSG_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. Note: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. |
6:5 |
RSVD |
R |
Reserved bits |
|
4:2 |
PROTCTL |
RW |
0x1 |
Protection control bits used to drive the AHB HPROT[3:1] bus. The AMBA specification recommends that the default of HPROT indicate a non-cached, non-buffered, and privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows:
|
1 |
FIFO_MODE |
RW |
0x0 |
FIFO mode select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. Value:
|
0 |
FCMODE |
RW |
0x0 |
Flow control mode. Determines when source transaction requests are serviced when the destination peripheral is the flow controller. Value:
|
Interrupt Registers
DMA_RAW_TFR
-
Name: Raw Status for Transfer Complete Interrupt
-
Description: Interrupt events are stored in this Raw Interrupt Status Register before masking. This register has a bit allocated to each channel; for example, DMA_RAW_TFR[2] is the Channel 2 raw transfer complete interrupt. Each bit in this register is cleared by writing a 1 to the corresponding location in the DMA_CLR_TFR register.
Note:Write access is available to this register or software for testing purposes only. Under normal operation, writes to this register are not recommended.
-
Base Address: 0x40014000
-
Offset: 0x2c0
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD |
R |
Reserved bits |
|
4:0 |
RAW_TFR |
RW |
0x0 |
Raw status for transfer complete interrupt Value:
|
DMA_RAW_BLK
-
Name: Raw Status for Block Transfer Complete Interrupt
-
Description: Interrupt events are stored in this Raw Interrupt Status Register before masking. This register has a bit allocated to each channel; for example, DMA_RAW_BLK[2] is the Channel 2 raw block complete interrupt. Each bit in this register is cleared by writing a 1 to the corresponding location in the CLR_BLK register.
Note:Write access is available to this register or software for testing purposes only. Under normal operation, writes to this register are not recommended.
-
Base Address: 0x40014000
-
Offset: 0x2c8
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD |
R |
Reserved bits |
|
4:0 |
RAW_BLK |
RW |
0x0 |
Raw Status for Block Transfer Complete Interrupt Value:
|
DMA_RAW_SRC_TRN
-
Name: Raw Status for Source Transaction Complete Interrupt
-
Description: Interrupt events are stored in this Raw Interrupt Status Register before masking. This register has a bit allocated to each channel; for example, DMA_RAW_SRC_TRN[2] is the Channel 2 raw source transaction complete interrupt. Each bit in this register is cleared by writing a 1 to the corresponding location in the DMA_CLR_DST_TRN register.
Note:Write access is available to this register or software testing purposes only. Under normal operation, writes to this register are not recommended.
-
Base Address: 0x40014000
-
Offset: 0x2D0
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD |
R |
Reserved bits |
|
4:0 |
SRC_TRN |
RW |
0x0 |
Raw status for source transaction complete interrupt Value:
|
DMA_RAW_DST_TRN
-
Name: Raw Status for Destination Transaction Complete Interrupt
-
Description: Interrupt events are stored in this Raw Interrupt Status register before masking. This register has a bit allocated to each channel; for example, DMA_RAW_DST_TRN[2] is the Channel 2 raw destination transaction complete interrupt. Each bit in this register is cleared by writing a 1 to the corresponding location in the DMA_CLR_DST_TRN register.
Note:Write access is available to this register or software testing purposes only. Under normal operation, writes to this register are not recommended.
-
Base Address: 0x40014000
-
Offset: 0x2d8
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD_ |
R |
Reserved bits |
|
4:0 |
DST_TRN |
RW |
0x0 |
Raw status for destination transaction complete interrupt Value:
|
DMA_RAW_ERR
-
Name: Raw Status for Error Interrupt
-
Description: Interrupt events are stored in this Raw Interrupt Status Register before masking. This register has a bit allocated to each channel; for example, DMA_RAW_ERR[2] is the Channel 2 raw error interrupt. Each bit in this register is cleared by writing a 1 to the corresponding location in the DMA_CLR_ERR register.
Note:Write access is available to this register or software testing purposes only. Under normal operation, writes to this register are not recommended.
-
Base Address: 0x40014000
-
Offset: 0x2E0
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD |
R |
Reserved bits |
|
4:0 |
RAW_ERR |
RW |
0x0 |
Raw Status for Error Interrupt Value:
|
DMA_STAT_TFR
-
Name: Status for Transfer Complete Interrupt
-
Description: Channel DMA transfer complete interrupt events from all channels are stored in this interrupt status register after masking. This register has a bit allocated to each channel; for example, DMA_STAT_TFR[2] is the Channel 2 source DMA transfer complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
-
Base Address: 0x40014000
-
Offset: 0x2E8
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD |
R |
Reserved bits |
|
4:0 |
STAT_TFR |
R |
0x0 |
Status for transfer complete interrupt Value:
|
DMA_STAT_BLK
-
Name: Status for Block Transfer Complete Interrupt
-
Description: Channel block complete interrupt events from all channels are stored in this interrupt status register after masking. This register has a bit allocated to each channel; for example, DMA_STAT_BLK[2] is the Channel 2 block complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
-
Base Address: 0x40014000
-
Offset: 0x2F0
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD_ |
R |
Reserved bits |
|
4:0 |
STAT_BLK |
R |
0x0 |
Status for block transfer complete interrupt Value:
|
DMA_STAT_SRC_TRN
-
Name: Status for Source Transaction Complete Interrupt
-
Description: Channel source transaction complete interrupt events from all channels are stored in this interrupt status register after masking. This register has a bit allocated to each channel; for example, DMA_STAT_SRC_TRN[2] is the Channel 2 source transaction complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
-
Base Address: 0x40014000
-
Offset: 0x2F8
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD_ |
R |
Reserved bits |
|
4:0 |
SRC_TRN |
R |
0x0 |
Status for source transaction complete interrupt Value:
|
DMA_STAT_DST_TRN
-
Name: Status for Destination Transaction Complete Interrupt
-
Description: Channel destination transaction complete interrupt events from all channels are stored in this interrupt status register after masking. This register has a bit allocated to each channel; for example, DMA_STAT_DST_TRN[2] is the Channel 2 status destination transaction complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
-
Base Address: 0x40014000
-
Offset: 0x300
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD_ |
R |
Reserved bits |
|
4:0 |
DST_TRN |
R |
0x0 |
Status for destination transaction complete interrupt Value:
|
DMA_STAT_ERR
-
Name: Status for Error Interrupt
-
Description: Channel error interrupt events from all channels are stored in this interrupt status register after masking. This register has a bit allocated to each channel; for example, DMA_STAT_ERR[2] is the Channel 2 status error interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
-
Base Address: 0x40014000
-
Offset: 0x308
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD |
R |
Reserved bits |
|
4:0 |
STAT_ERR |
R |
0x0 |
Status for error interrupt Value:
|
DMA_MASK_TFR
-
Name: MASK for Transfer Complete Interrupt
-
Description: The contents of the raw status register DMA_RAW_TFR are masked with the contents of the mask register DMA_MASK_TFR. This register has a bit allocated to each channel; for example, DMA_MASK_TFR[2] is the mask bit for the Channel 2 transfer complete interrupt. A channel MASK_TFR bit will be written only if the corresponding mask write enable bit in the MASK_TFR_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the DMA_MASK_TFR register writes a 1 into DMA_MASK_TFR[0], while DMA_MASK_TFR[7:1] remains unchanged. Writing hex 00xx leaves DMA_MASK_TFR[7:0] unchanged. Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the status registers and int_port signals.
-
Base Address: 0x40014000
-
Offset: 0x310
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
RSVD_ |
R |
Reserved bits |
|
12:8 |
MASK_TFR_WE |
W |
0x0 |
Interrupt Mask Write Enable Value:
|
7:5 |
RSVD_ |
R |
Reserved bits |
|
4:0 |
MASK_TFR |
RW |
0x0 |
Mask for Transfer Complete Interrupt Value:
|
DMA_MASK_BLK
-
Name: Mask for Block Transfer Complete Interrupt
-
Description: The contents of the raw status register DMA_RAW_BLK are masked with the contents of the mask register DMA_MASK_BLK. This register has a bit allocated to each channel; for example, DMA_MASK_BLK[2] is the mask bit for the Channel 2 block complete interrupt. A channel MASK_TFR bit will be written only if the corresponding mask write enable bit in the MASK_TFR_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the DMA_MASK_BLK register writes a 1 into DMA_MASK_BLK[0], while DMA_MASK_BLK[7:1] remains unchanged. Writing hex 00xx leaves DMA_MASK_BLK[7:0] unchanged. Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the status registers and int_port signals.
-
Base Address: 0x40014000
-
Offset: 0x318
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
RSVD_ |
R |
Reserved bits |
|
12:8 |
MASK_BLK_WE |
W |
0x0 |
Interrupt Mask Write Enable Value:
|
7:5 |
RSVD_ |
R |
Reserved bits |
|
4:0 |
MASK_BLK |
RW |
0x0 |
Mask for Block Transfer Complete Interrupt Value:
|
DMA_MASK_SRC_TRN
-
Name: MASK for Source Transaction Complete Interrupt
-
Description: The contents of the raw status register DMA_RAW_SRC_TRN are masked with the contents of the mask register DMA_MASK_SRC_TRN. This register has a bit allocated to each channel; for example, DMA_MASK_SRC_TRN[2] is the mask bit for the Channel 2 source transaction complete interrupt. When the source peripheral of DMA channel i is memory, then the source transaction complete interrupt, DMA_MASK_SRC_TRN[i], must be masked to prevent an erroneous triggering of an interrupt on the int_combined signal. A channel MASK_TFR bit will be written only if the corresponding mask write enable bit in the MASK_TFR_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the DMA_MASK_SRC_TRN register writes a 1 into DMA_MASK_SRC_TRN[0], while DMA_MASK_SRC_TRN[7:1] remains unchanged. Writing hex 00xx leaves DMA_MASK_SRC_TRN[7:0] unchanged. Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the status registers and int_port signals.
-
Base Address: 0x40014000
-
Offset: 0x320
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
RSVD_ |
R |
Reserved bits |
|
12:8 |
SRC_TRN_WE |
W |
0x0 |
Interrupt Mask Write Enable Value:
|
7:5 |
RSVD_ |
R |
Reserved bits |
|
4:0 |
MASK_SRC_TRN |
RW |
0x0 |
Mask for Source Transaction Complete Interrupt Value:
|
DMA_MASK_DST_TRN
-
Name: Mask for Destination Transaction Complete Interrupt
-
Description: The contents of the raw status register DMA_RAW_DST_TRN are masked with the contents of the mask register DMA_MASK_DST_TRN. This register has a bit allocated to each channel; for example, DMA_MASK_DST_TRN[2] is the mask bit for the Channel 2 destination transaction complete interrupt. When the destination peripheral of DMA channel i is memory, then the destination transaction complete interrupt, DMA_MASK_DST_TRN[i], must be masked to prevent an erroneous triggering of an interrupt on the int_combined(_n) signal. A channel MASK_TFR bit will be written only if the corresponding mask write enable bit in the MASK_TFR_W field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the DMA_MASK_DST_TRN register writes a 1 into DMA_MASK_DST_TRN[0], while DMA_MASK_DST_TRN[7:1] remains unchanged. Writing hex 00xx leaves DMA_MASK_DST_TRN[7:0] unchanged. Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the status registers and int_port signals.
-
Base Address: 0x40014000
-
Offset: 0x328
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
RSVD_ |
R |
Reserved bits |
|
12:8 |
MASK_DST_TRN_WE |
W |
0x0 |
Interrupt Mask Write Enable Value:
|
7:5 |
RSVD_ |
R |
Reserved bits |
|
4:0 |
MASK_DST_TRN |
RW |
0x0 |
Mask for Destination Transaction Complete Interrupt Value:
|
DMA_MASK_ERR
-
Name: Mask for Error Interrupt
-
Description: The contents of the raw status register DMA_RAW_ERR are masked with the contents of the mask register DMA_MASK_ERR. This register has a bit allocated to each channel; for example, DMA_MASK_ERR[2] is the mask bit for the Channel 2 error interrupt. A channel MASK_TFR bit will be written only if the corresponding mask write enable bit in the MASK_TFR_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the DMA_MASK_ERR register writes a 1 into DMA_MASK_ERR[0], while DMA_MASK_ERR[7:1] remains unchanged. Writing hex 00xx leaves DMA_MASK_ERR[7:0] unchanged. Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the Status registers and int_port signals.
-
Base Address: 0x40014000
-
Offset: 0x330
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
RSVD_ |
R |
Reserved bits |
|
12:8 |
MASK_ERR_WE |
W |
0x0 |
Interrupt Mask Write Enable Value:
|
7:5 |
RSVD_ |
R |
Reserved bits |
|
4:0 |
MASK_ERR |
RW |
0x0 |
Mask for Error Interrupt Value:
|
DMA_CLR
- Name: Clear for Transfer Complete Interrupt
-
Description: Each bit in the DMA_RAW_TFR and DMA_STAT_TFRis cleared on the same cycle by writing a 1 to the corresponding location in the registers. This register has a bit allocated to each channel; for example, DMA_CLR_TFR[2] is the clear bit for the Channel 2 transfer done interrupt. Writing a 0 has no effect. This register is not readable.
-
Base Address: 0x40014000
-
Offset: 0x338
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD_ |
W |
Reserved bits |
|
4:0 |
CLR_TFR |
W |
0x0 |
Clear for Transfer Complete Interrupt Value:
|
DMA_CLR_BLK
-
Name: Clear for Block Transfer Complete Interrupt
-
Description: Each bit in the DMA_RAW_BLK and DMA_STAT_BLK is cleared on the same cycle by writing a 1 to the corresponding location in the registers. This register has a bit allocated to each channel; for example, DMA_CLR_BLK[2] is the clear bit for the Channel 2 block done interrupt. Writing a 0 has no effect. This register is not readable.
-
Base Address: 0x40014000
-
Offset: 0x340
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD_ |
W |
Reserved bits |
|
4:0 |
CLR_BLK |
W |
0x0 |
Clear for Block Transfer Complete Interrupt |
DMA_CLR_SRC_TRN
-
Name: Clear for Source Transaction Complete Interrupt
-
Description: Each bit in the DMA_RAW_SRC_TRN and DMA_STAT_SRC_TRN is cleared on the same cycle by writing a 1 to the corresponding location in the registers. This register has a bit allocated to each channel; for example, DMA_CLR_DST_TRN[2] is the clear bit for the Channel 2 source transaction done interrupt. Writing a 0 has no effect. This register is not readable.
-
Base Address: 0x40014000
-
Offset: 0x348
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD |
W |
Reserved bits |
|
4:0 |
CLR_SRC_TRN |
W |
0x0 |
Clear for Source Transaction Complete Interrupt Value:
|
DMA_CLR_DST_TRN
-
Name: Clear for Destination Transaction Complete Interrupt
-
Description: Each bit in the DMA_RAW_DST_TRN and DMA_STAT_DST_TRN is cleared on the same cycle by writing a 1 to the corresponding location in the registers. This register has a bit allocated to each channel; for example, DMA_CLR_DST_TRN[2] is the clear bit for the Channel 2 destination transaction done interrupt. Writing a 0 has no effect. This register is not readable.
-
Base Address: 0x40014000
-
Offset: 0x350
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD_ |
W |
0x0 |
Reserved bits |
4:0 |
CLR_DST_TRN |
W |
0x0 |
Clear for Destination Transaction Complete Interrupt Value:
|
DMA_CLR_ERR
-
Name: Clear for Error Interrupt
-
Description: Each bit in the DMA_RAW_ERR and DMA_STAT_ERR is cleared on the same cycle by writing a 1 to the corresponding location in the registers. This register has a bit allocated to each channel; for example, DMA_CLR_ERR[2] is the clear bit for the Channel 2 error interrupt. Writing a 0 has no effect. This register is not readable.
-
Base Address: 0x40014000
-
Offset: 0x358
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD_ |
W |
Reserved bits |
|
4:0 |
CLR_ERR |
W |
0x0 |
Clear for Error Interrupt Value:
|
DMA_STATUS_INT
-
Name: Status for Each Interrupt Type
-
Description: The contents of each of the five status registers DMA_STAT_SRC_TRN, DMA_STAT_BLK, DMA_STAT_SRC_TRN, DMA_STAT_DST_TRN, and DMA_STAT_ERR are ORed to produce a single bit for each interrupt type in the combined status register (DMA_STATUS_INT). This register is read-only.
-
Base Address: 0x40014000
-
Offset: 0x360
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:5 |
RSVD_ |
R |
Reserved bits |
|
4 |
ERR |
R |
0x0 |
OR of the contents of DMA_STAT_ERR Value:
|
3 |
DST |
R |
0x0 |
OR of the contents of DMA_STAT_DST_TRN Value:
|
2 |
SRC |
R |
0x0 |
OR of the contents of DMA_STAT_SRC_TRN Value:
|
1 |
BLK |
R |
0x0 |
OR of the contents of DMA_STAT_BLK register Value:
|
0 |
TFR |
R |
0x0 |
OR of the contents of DMA_STAT_TFR register Value:
|
Software Handshake Registers
REQ_SRC
-
Name: Source Software Transaction Request Register
-
Description: A bit is assigned for each channel in this register. REQ_SRC[n] is ignored when software handshaking is not enabled for the source of channel n. A channel SRC_REQ bit is written only if the corresponding channel write enable bit in the SRC_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register. For example, writing hex 0101 writes a 1 into REQ_SRC[0], while REQ_SRC[7:1] remains unchanged. Writing hex 00xx leaves REQ_SRC[7:0] unchanged. This allows software to set a bit in the REQ_SRC register without performing a read-modified write operation.
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Base Address: 0x40014000
-
Offset: 0x368
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
RSVD |
R |
Reserved bits |
|
12:8 |
SRC_REQ_WE |
RW |
0x0 |
Source Software Transaction Request write enable Value:
|
7:5 |
RSVD |
R |
Reserved bits |
|
4:0 |
SRC_REQ |
RW |
0x0 |
Source Software Transaction Request Value:
|
REQ_DST
-
Name: Destination Software Transaction Request Register
-
Description: A bit is assigned for each channel in this register. REQ_DST[n] is ignored when software handshaking is not enabled for the source of channel n. A channel DEST bit is written only if the corresponding channel write enable bit in the DEST_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
-
Base Address: 0x40014000
-
Offset: 0x370
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
RSVD |
R |
Reserved bits |
|
12:8 |
DEST_REQ_WE |
RW |
0x0 |
Destination Software Transaction Request write enable Value:
|
7:5 |
RSVD |
R |
Reserved bits |
|
4:0 |
DEST_REQ |
RW |
0x0 |
Destination Software Transaction Request Value:
|
SGL_RQ_SRC
-
Name: Source Single Transaction Request Register
-
Description: A bit is assigned for each channel in this register. SGL_RQ_SRC is ignored when software handshaking is not enabled for the source of channel n. A channel SRC_SGL_REQ bit is written only if the corresponding channel write enable bit in the SRC_SGL_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
-
Base Address: 0x40014000
-
Offset: 0x378
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
RSVD |
R |
Reserved bits |
|
12:8 |
SRC_SGL_REQ_WE |
RW |
0x0 |
Source Single Transaction Request write enable Value:
|
7:5 |
RSVD |
R |
Reserved bits |
|
4:0 |
SRC_SGL_REQ |
RW |
0x0 |
Source Single Transaction Request Value:
|
SGL_RQ_DST
- Name: Destination Single Transaction Request Register
- Description: A bit is assigned for each channel in this register. SGL_RQ_DST is ignored when software handshaking is not enabled for the destination of channel n. A channel DEST_SGL_REQ bit is written only if the corresponding channel write enable bit in the DST_SGL_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
- Base Address: 0x4A0014000
- Offset: 0x380
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
Rsvd_1_ |
R |
Reserved bits |
|
12:8 |
DST_SGL_REQ_WE |
RW |
0x0 |
Destination Single Transaction Request write enable Value:
|
7:5 |
Rsvd_1_ |
R |
Reserved bits |
|
4:0 |
DEST_SGL_REQ |
RW |
0x0 |
Destination Single Transaction Request Value:
|
LST_SRC
- Name: Source Last Transaction Request Register
- Description: A bit is assigned for each channel in this register. LST_SRC is ignored when software handshaking is not enabled for the source of channel n, or when the source of channel n is not a flow controller. A channel LST_SRC bit is written only if the corresponding channel write enable bit in the LST_SRC_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
- Base Address: 0x40014000
- Offset: 0x388
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
Rsvd_1_ |
R |
Reserved bits |
|
12:8 |
LST_SRC_WE |
RW |
0x0 |
Source Last Transaction Request write enable Value:
|
7:5 |
Rsvd_1_ |
R |
Reserved bits |
|
4:0 |
LST_SRC |
RW |
0x0 |
Source Last Transaction Request register Value:
|
LST_DST
-
Name: Destination Last Transaction Request Register
-
Description: A bit is assigned for each channel in this register. LST_DST is ignored when software handshaking is not enabled for the destination of channel n or when the destination of channel n is not a flow controller. A channel LST_DEST bit is written only if the corresponding channel write enable bit in the LST_DEST_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
-
Base Address: 0x40014000
-
Offset: 0x390
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
Rsvd_1_ |
R |
Reserved bits |
|
12:8 |
LST_DEST_WE |
RW |
0x0 |
Destination Last Transaction Request write enable Value:
|
7:5 |
Rsvd_1_ |
R |
Reserved bits |
|
4:0 |
LST_DEST |
RW |
0x0 |
Destination Last Transaction Request Value:
|
Miscellaneous Registers
CFG
-
Name: DMA Configuration Register
-
Description: This register is used to enable the DMA, which must be done before any channel activity. If the global channel enable bit is cleared while any channel is still active, CFG. EN still returns 1 to indicate that there are channels still active until hardware has terminated all activities on all channels, at which point the CFG. EN bit returns 0.
-
Base Address: 0x40014000
-
Offset: 0x398
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:1 |
RSVD |
R |
Reserved bits |
|
0 |
EN |
RW |
0x0 |
DMA Enable bit. Value:
|
CH_EN
-
Name: DMA Channel Enable Register
-
Description: This is the DMA Channel Enable Register. If software needs to set up a new channel, it can read this register in order to find out which channels are currently inactive; it can then enable an inactive channel with the required priority. All bits of this register are cleared to 0 when the global DMA channel enable bit, CFG[0], is 0. When the global channel enable bit is 0, a write to the CH_EN register is ignored and a read will always read back 0. The channel enable bit, CH_EN.CH_EN, is written only if the corresponding channel write enable bit, CH_EN. CH_WE_EN, is asserted on the same AHB write transfer. For example, writing hex 01x1 writes a 1 into CH_EN[0], while CH_EN[7:1] remains unchanged. Writing hex 00xx leaves CH_EN[7:0] unchanged. Note that a read-modified write is not required.
-
Base Address: 0x40014000
-
Offset: 0x3a0
-
Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
63:13 |
RSVD |
R |
Reserved bits |
|
12:8 |
CH_WE_EN |
W |
0x0 |
Channel enable register |
7:5 |
RSVD |
R |
Reserved bits |
|
4:0 |
CH_EN |
RW |
0x0 |
Channel Enable. The CH_EN.CH_EN bit is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer. Value:
|
