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GR533x Datasheet

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V1.2

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文档中心 > GR533x Datasheet/ System/ Registers/ MCU Subsystem Copy URL

MCU Subsystem

BLE_FERP_CTL

Name: BLE_FERP_CTL Register
Description: BLE_FERP_CTL Register
Base Address: 0x4000E000
Offset: 0x224
Reset Value: 0x00000000

Table 193 BLE_FERP_CTL Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R	0x0	Reserved bits
0	FERP_EN	RW	0x0	Enable ferp memory clock & ferp memory access on SoC side by configuring this register to 1 before starting a 2.4G spec use.

SECURITY_RESET

Name: SECURITY_RESET Register
Description: SECURITY_RESET Register
Base Address: 0x4000E000
Offset: 0x22C
Reset Value: 0x00000028

Table 194 SECURITY_RESET Register
Bits	Field Name	RW	Reset	Description
31:6	RSVD	R	0x0	Reserved bits
5	TRNG	RW	0x1	TRNG soft reset, low active Value: 0x0: reset module 0x1: normal work mode
4	RSVD	R	0x0	Reserved bit
3	EFUSE	RW	0x1	eFuse controller soft reset, low active Value: 0x0: reset module 0x1: normal work mode
2:0	RSVD	R	0x0	Reserved bits

PMU_ID

Name: PMU_ID Register
Description: PMU_ID Register
Base Address: 0x4000E000
Offset: 0x230
Reset Value: 0x000000B0

Table 195 PMU_ID Register
Bits	Field Name	RW	Reset	Description
31:8	RSVD	R	0x0	Reserved bits
7:0	PMU_ID	R	0xB0	PMU chip ID

PWR_AVG_CTL_REG0

Name: PWR_AVG_CTL_REG0 Register
Description: PWR_AVG_CTL_REG0 Register
Base Address: 0x4000E000
Offset: 0x234
Reset Value: 0x00000004

Table 196 PWR_AVG_CTL_REG0 Register
Bits	Field Name	RW	Reset	Description
31:24	TPA_ADC_OUT	R	0x0	Real-time value
18	AVG_PWR_ERR	R	0x0	Indicate ble_tx_en going off before outputting the result.
17	RSVD	R	0x0	Reserved bit
16	AVG_PWR_RDY	R	0x0	Indicate that the average value is ready to read.
15:8	AVG_PWR	R	0x0	Average power data
7:4	SAMPL_PWR	RW	0x0	Take 2 ^ n samples for averaging (0–15).
3	BLE_F_TX_EN	RW	0x0	Forcibly enable internal ble_tx_en.
2	ONESHOT_EN	RW	0x1	Enable one shot mode.
1	RSVD	R	0x0	Reserved bit
0	PWR_AVG_EN	RW	0x0	Enable the power average calculation block.

TIMER2BLE_PLUSE_CTRL

Name: TIMER2BLE_PLUSE_CTRL Register
Description: TIMER2BLE_PLUSE_CTRL Register
Base Address: 0x4000E000
Offset: 0x238
Reset Value: 0x00000000

Table 197 TIMER2BLE_PLUSE_CTRL Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1:0	TIMER2BLE_PLUSE_CTRL	RW	0x0	Bluetooth LE pulse selection control: Value: 0x0: timer1 0x1: timer2 0x2: dual timer fr1 0x3: dual timer fr2

EFUSE_PWR_DELTA_0

Name: EFUSE_PWR_DELTA_0 Register
Description: EFUSE_PWR_DELTA_0 Register
Base Address: 0x4000E000
Offset: 0x254
Reset Value: 0x0FFF00B4

Table 198 EFUSE_PWR_DELTA_0 Register
Bits	Field Name	RW	Reset	Description
31:16	DELTA1	RW	0xFFF	About 250 μs; an eFuse power controller timing parameter; based on 16 MHz clock
15:0	DELTA0	RW	0xB4	About 10 μs; an eFuse power controller timing parameter; based on 16 MHz clock

EFUSE_PWR_DELTA_1

Name: EFUSE_PWR_DELTA_1 Register
Description: EFUSE_PWR_DELTA_1 Register
Base Address: 0x4000E000
Offset: 0x258
Reset Value: 0x000000B4

Table 199 EFUSE_PWR_DELTA_1 Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R	0x0	Reserved bits
15:0	DELTA2	RW	0xB4	About 10 μs; an eFuse power controller timing parameter; based on 16 MHz clock

EFUSE_PWR_CTRL_0

Name: EFUSE_PWR_CTRL_0 Register
Description: EFUSE_PWR_CTRL_0 Register
Base Address: 0x4000E000
Offset: 0x260
Reset Value: 0x00000000

Table 200 EFUSE_PWR_CTRL_0 Register
Bits	Field Name	RW	Reset	Description
31:5	RSVD	R	0x0	Reserved bits
4	STP	RW	0x0	Write 1 to stop the power sequencer.
3	RSVD	R	0x0	Reserved bit
2	BGN	RW	0x0	Write 1 to begin the power sequencer.
1	RSVD	R	0x0	Reserved bit
0	EN	RW	0x0	Enable the eFuse controller.

EFUSE_PWR_CTRL_1

Name: EFUSE_PWR_CTRL_1 Register
Description: EFUSE_PWR_CTRL_1 Register
Base Address: 0x4000E000
Offset: 0x264
Reset Value: 0x00000000

Table 201 EFUSE_PWR_CTRL_1 Register
Bits	Field Name	RW	Reset	Description
31:5	RSVD	R	0x0	Reserved bits
4	DIS_DONE	R	0x0	eFuse power disable done. Clear on read.
3:1	RSVD	R	0x0	Reserved bits
0	EN_DONE	R	0x0	eFuse power enable done. Clear on read.

MCU_BOOT_DBG

Name: MCU_BOOT_DBG Register
Description: MCU_BOOT_DBG Register
Base Address: 0x4000E000
Offset: 0x27C
Reset Value: 0x00000000

Table 202 MCU_BOOT_DBG Register
Bits	Field Name	RW	Reset	Description
31:0	MCU_BOOT_DBG	RW	0x0	MCU boot debug register; record the boot status.

MCU_SUB_REG

Name: MCU_SUB_REG Register
Description: MCU_SUB_REG Register
Base Address: 0x4000E000
Offset: 0x280
Reset Value: 0x00000000

Table 203 MCU_SUB_REG Register
Bits	Field Name	RW	Reset	Description
31:14	RSVD	R	0x0	Reserved bits
13:12	GDX_REG_WAIT_STATE	RW	0x0	ROM AHB wait state number
11:6	RSVD	R	0x0	Reserved bits
5:4	MEM_BOND_OPT	R	0x0	Value: 0x0: 80 KB (SRAMs 0–4 ON) 0x1: 64 KB (SRAMs 0–3 ON; SRAM 4 OFF) 0x2: 48 KB (SRAMs 0–2 ON; SRAMs 3–4 OFF) 0x3: 32 KB (SRAMs 0–1 ON; SRAMs 2–4 OFF)
3:0	RSVD	R	0x0	Reserved bits

MCU_NMI_CFG

Name: MCU_NMI_CFG Register
Description: MCU_NMI_CFG Register
Base Address: 0x4000E000
Offset: 0x284
Reset Value: 0x00000000

Table 204 MCU_NMI_CFG Register
Bits	Field Name	RW	Reset	Description
31:10	RSVD	R	0x0	Reserved bits
9:0	MCU_NMI_SEL	RW	0x0	Select MCU NMI. bit9: aon_irq_sts[IRQ_BLE_PWR_DN_DONE] bit8: aon_irq_sts[IRQ_BLE_PWR_UP_DONE] bit7: timer0_irq bit6: aon_evts[EVT_CLDR_TIMER_EVT_0] bit5: aon_evts[EVT_WD_TIMER_ALMOST_EXP] bit4: aon_evts[EVT_SMC_OSC_EN] bit3: aon_irq_sts[IRQ_PMU_BOD_REDGA] bit2: aon_evts[EVT_BLE_MAC_IRQ] bit1: gpio_1_irq bit0: gpio_0_irq

CPLL_IRQ_CFG

Name: CPLL_IRQ_CFG Register
Description: CPLL_IRQ_CFG Register
Base Address: 0x4000E000
Offset: 0x288
Reset Value: 0x00000000

Table 205 CPLL_IRQ_CFG Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R	0x0	Reserved bits
0	DRIFT_IRQ_EN	RW	0x0	Enable CPLL drift IRQ.

AON_SW_RST

Name: AON_SW_RST Register
Description: AON_SW_RST Register
Base Address: 0x4000E000
Offset: 0x28C
Reset Value: 0xC5A10000

Table 206 AON_SW_RST Register
Bits	Field Name	RW	Reset	Description
31:16	SET	W	0xC5A1	Reserved bits
15:9	RSVD	R	0x0	Always-on software reset magic word for enabling configuration.
8	FULL	W	0x0	Always-on software reset for full logic
7:1	RSVD	R	0x0	Reserved bits
0	PARTIAL	W	0x0	Always-on software reset for partial logic

MCU_SUBSYS_CG_CTRL[0]

Name: MCU_SUBSYS_CG_CTRL[0] Register
Description: MCU_SUBSYS_CG_CTRL[0] Register
Base Address: 0x4000E000
Offset: 0x2C0
Reset Value: 0x00000000

Table 207 MCU_SUBSYS_CG_CTRL[0] Register
Bits	Field Name	RW	Reset	Description
31:11	RSVD	R	0x0	Reserved bits
10	WFI_SERIAL_HCLK	RW	0x0	HCLK for serial blocks including I2C, UART, QSPI, and SPI (M & S) Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.
9	WFI_APB_SUB_HCLK	RW	0x0	HCLK for APB subsystem including watchdog and timer Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.
8	WFI_BLE_BRG_HCLK	RW	0x0	HCLK for Bluetooth LE MCU bridge Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.
7	RSVD	R	0x0	Reserved bits
6	WFI_GPIO_HCLK	RW	0x0	HCLK for GPIOs Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.
5	WFI_SNSADC_HCLK	RW	0x0	HCLK for sense ADC Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.
4	WFI_ROM_HCLK	RW	0x0	HCLK for ROM Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.
3	RSVD	R	0x0	Reserved bits
2	WFI_HTB_HCLK	RW	0x0	HCLK for hopping table Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.
1	RSVD	R	0x0	Reserved bits
0	WFI_SECU_HCLK	RW	0x0	HCLK for all security blocks including eFuse and TRNG Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.

MCU_SUBSYS_CG_CTRL[1]

Name: MCU_SUBSYS_CG_CTRL[1] Register
Description: MCU_SUBSYS_CG_CTRL[1] Register
Base Address: 0x4000E000
Offset: 0x2C4
Reset Value: 0x0000FFEF

Table 208 MCU_SUBSYS_CG_CTRL[1] Register
Bits	Field Name	RW	Reset	Description
31:11	RSVD	R	0x0	Reserved bits
10	FORCE_SERIAL_HCLK	RW	0x1	HCLK for serial blocks including I2C, UART, QSPI, and SPI (M & S) Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
9	FORCE_APB_SUB_HCLK	RW	0x1	HCLK for APB subsystem including watchdog and timer Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
8	FORCE_BLE_BRG_HCLK	RW	0x1	HCLK for Bluetooth LE MCU bridge Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
7	RSVD	R	0x0	Reserved bits
6	FORCE_GPIO_HCLK	RW	0x1	HCLK for GPIOs Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
5	FORCE_SNSADC_HCLK	RW	0x1	HCLK for sense ADC Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
4	FORCE_ROM_HCLK	RW	0x0	HCLK for ROM Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
3	RSVD	R	0x0	Reserved bits
2	FORCE_HTB_HCLK	RW	0x1	HCLK for hopping table Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
1	RSVD	R	0x1	Reserved bits
0	FORCE_SECU_HCLK	RW	0x1	HCLK for all security blocks including eFuse and TRNG Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.

MCU_SUBSYS_CG_CTRL[2]

Name: MCU_SUBSYS_CG_CTRL[2] Register
Description: MCU_SUBSYS_CG_CTRL[2] Register
Base Address: 0x4000E000
Offset: 0x2C8
Reset Value: 0x00020000

Table 209 MCU_SUBSYS_CG_CTRL[2] Register
Bits	Field Name	RW	Reset	Description
31:19	RSVD	R	0x0	Reserved bits
18	FORCE_SRAM_HCLK	RW	0x0	SRAM HCLK clock Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
17	FORCE_XF_XQSPI_HCLK	RW	0x1	Cache HCLK clock Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
16:3	RSVD	R	0x0	Reserved bits
2	WFI_SRAM_HCLK	RW	0x0	SRAM HCLK clock during WFI Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.
1	WFI_XF_XQSPI_HCLK	RW	0x0	Cache HCLK clock during WFI Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.
0	WFI_AON_MCUSUB_HCLK	RW	0x0	mcu_reg_hclk clock during WFI Value: 0x0: HCLK is always on. 0x1: HCLK is gated during WFI/WFE.

MCU_PERIPH_PCLK_OFF

Name: MCU_PERIPH_PCLK_OFF Register
Description: MCU_PERIPH_PCLK_OFF Register
Base Address: 0x4000E000
Offset: 0x2CC
Reset Value: 0x30063005

Table 210 MCU_PERIPH_PCLK_OFF Register
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R	0x0	Reserved bits
29	FORCE_PWM_1_PCLK	RW	0x1	pwm_1 CLK Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
28	FORCE_PWM_0_PCLK	RW	0x1	pwm_0 CLK Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
27:19	RSVD	R	0x0	Reserved bits
18	FORCE_SPI_S_PCLK	RW	0x1	spi_s CLK Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
17	FORCE_SPI_M_PCLK	RW	0x1	spi_m CLK Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
16:4	RSVD	R	0x0	Reserved bits
13	FORCE_I2C1_PCLK	RW	0x1	i2c_1 CLK Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
12	FORCE_I2C0_PCLK	RW	0x1	i2c_0 CLK Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
11:3	RSVD	R	0x0	Reserved bits
2	FORCE_UART1_PCLK	RW	0x1	uart_1 CLK Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
1	RSVD	R	0x0	Reserved bit
0	FORCE_UART0_PCLK	RW	0x1	uart_0 CLK Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.

MCU_PERIPH_CG_LP_EN

Name: MCU_PERIPH_CG_LP_EN Register
Description: MCU_PERIPH_CG_LP_EN Register
Base Address: 0x4000E000
Offset: 0x2D0
Reset Value: 0x000007FF

Table 211 MCU_PERIPH_CG_LP_EN Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R	0x0	Reserved bits
10	AHB2APB_ASYNC_BRG_LP_EN	RW	0x1	Enable apb2apb async bridge low-power feature.
9	AHB2APB_BRG_LP_EN	R	0x1	Enable ahb2apb bridge low-power feature.
8	AHB_BUS_LP_EN	RW	0x1	Enable AHB bus low-power feature.
7	I2C1_LP_SCLK_EN	R	0x1	Enable i2c1 SCLK low-power feature.
6	I2C0_LP_SCLK_EN	R	0x1	Enable i2c0 SCLK low-power feature.
5	SPIS_LP_SCLK_EN	RW	0x1	Enable SPIS SCLK low-power feature.
4	SPIM_LP_SCLK_EN	RW	0x1	Enable SPIM SCLK low-power feature.
3	UART1_LP_PCLK_EN	RW	0x1	Enable uart1 PCLK low-power feature.
2	UART1_LP_SCLK_EN	R	0x1	Enable uart1 SCLK low-power feature.
1	UART0_LP_PCLK_EN	RW	0x1	Enable uart0 PCLK low-power feature.
0	UART0_LP_SCLK_EN	RW	0x1	Enable uart0 SCLK low-power feature.

MCU_PERIPH_CLK_SLP_OFF

Name: MCU_PERIPH_CLK_SLP_OFF Register
Description: MCU_PERIPH_CLK_SLP_OFF Register
Base Address: 0x4000E000
Offset: 0x2D4
Reset Value: 0x00000000

Table 212 MCU_PERIPH_CLK_SLP_OFF Register
Bits	Field Name	RW	Reset	Description
31:14	RSVD	R	0x0	Reserved bits
13	PWM1	RW	0x0	Enable pwm_1 PCLK auto off when CPU is in sleep state.
12	PWM0	RW	0x0	Enable pwm_0 PCLK auto off when CPU is in sleep state.
11	SPIS	RW	0x0	Enable spi_s PCLK auto off when CPU is in sleep state.
10	SPIM	RW	0x0	Enable spi_m PCLK auto off when CPU is in sleep state.
9:8	RSVD	R	0x0	Reserved bits
7	I2C1	RW	0x0	Enable i2c_1 PCLK auto off when CPU is in sleep state.
6	I2C0	RW	0x0	Enable i2c_0 PCLK auto off when CPU is in sleep state.
5:2	RSVD	R	0x0	Reserved bits
1	UART1	RW	0x0	Enable uart_1 PCLK auto off when CPU is in sleep state.
0	UART0	RW	0x0	Enable uart_0 PCLK auto off when CPU is in sleep state.

SECU_CLK_CTRL

Name: SECU_CLK_CTRL Register
Description: SECU_CLK_CTRL Register
Base Address: 0x4000E000
Offset: 0x2D8
Reset Value: 0x00003C00

Table 213 SECU_CLK_CTRL Register
Bits	Field Name	RW	Reset	Description
31:14	RSVD	R	0x0	Reserved bits
13	EFUSE_HCLK_SLP_OFF	RW	0x1	Enable eFuse PCLK auto off when CPU is in sleep state.
12	EFUSE_HCLK_FORCE_OFF	RW	0x1	eFuse PCLK Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
11	RNG_HCLK_SLP_OFF	RW	0x1	Enable RNG PCLK auto off when CPU is in sleep state.
10	RNG_HCLK_FORCE_OFF	RW	0x1	RNG PCLK Value: 0x0: Force the clock to be ON. 0x1: Force the clock to be OFF.
9:0	RSVD	R	0x0	Reserved bits

MCU_MISC_CLK

Name: MCU_MISC_CLK Register
Description: MCU_MISC_CLK Register
Base Address: 0x4000E000
Offset: 0x2E8
Reset Value: 0x0000000C

Table 214 MCU_MISC_CLK Register
Bits	Field Name	RW	Reset	Description
31:4	RSVD	R	0x0	Reserved bits
3	DMA0_HCLK_OFF	RW	0x1	Value: 0x0: Turn on DMA CLK. 0x1: Turn off DMA CLK.
2	XQSPI_SCK_OFF	RW	0x1	Value: 0x0: Turn on XQSPI SPI CLK. 0x1: Turn off XQSPI SPI CLK.
1:0	RSVD	R	0x0	Reserved bits

HFOSC_CLK_EN

Name: HFOSC_CLK_EN Register
Description: HFOSC_CLK_EN Register
Base Address: 0x4000E000
Offset: 0x2F4
Reset Value: 0x00000001

Table 215 HFOSC_CLK_EN Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R	0x0	Reserved bits
0	EN	RW	0x1	Value: 0x0: Turn off HFOSC CLK. 0x1: Turn on HFOSC CLK.

APB_TIMER_DBG

Name: APB_TIMER_DBG Register
Description: APB_TIMER_DBG Register
Base Address: 0x4000E000
Offset: 0x340
Reset Value: 0x0000000F

Table 216 APB_TIMER_DBG Register
Bits	Field Name	RW	Reset	Description
31:4	RSVD	R	0x0	Reserved bits
3	WDT	RW	0x0	Write 1 to stop the watchdog timer during CPU HALT.
2	DUAL_TIMER	RW	0x0	Write 1 to stop the dual timer during CPU HALT.
1	TIMER1	RW	0x0	Write 1 to stop the timer1 during CPU HALT.
0	TIMER0	RW	0x0	Write 1 to stop the timer0 during CPU HALT.

APB_MON_DBG

Name: APB_MON_DBG Register
Description: APB_MON_DBG Register
Base Address: 0x4000E000
Offset: 0x344
Reset Value: 0x00000000

Table 217 APB_MON_DBG Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R	0x0	Reserved bits
0	BYPASS	RW	0x0	Write 1 to bypass AHB2APB bridge monitor.

MCU_RELEASE

Name: MCU_RELEASE Register
Description: MCU_RELEASE Register
Base Address: 0x4000E000
Offset: 0x380
Reset Value: 0x20220710

Table 218 MCU_RELEASE Register
Bits	Field Name	RW	Reset	Description
31:0	MCU_RELEASE	R	0x20220710	Contain the RTL release date.

FPGA_CTRL

Name: FPGA_CTRL Register
Description: FPGA_CTRL Register
Base Address: 0x4000E000
Offset: 0x384
Reset Value: 0x00000000

Table 219 FPGA_CTRL Register
Bits	Field Name	RW	Reset	Description
31:5	RSVD	R	0x0	Reserved bits
4	EXIST	R	0x0	This HW is 0: ASIC, 1: FPGA.
3:2	RSVD	R	0x0	Reserved bits
1:0	MUX_SEL	RW	0x0	Select FPGA debug port signals.

ST_CALIB

Name: ST_CALIB Register
Description: ST_CALIB Register
Base Address: 0x4000E000
Offset: 0x388
Reset Value: 0x0000013F

Table 220 ST_CALIB Register
Bits	Field Name	RW	Reset	Description
31:29	RSVD	R	0x0	Reserved bits
28	STCALIB_CLK	RW	0x0	mcu_stclk_sel Value: 0x0: rng_clk 0x1: xo_clk
27:26	RSVD	R	0x0	Reserved bits
25:0	STCALIB	RW	0x13F	STCAILIB to ARM Core STCLK = 32 KHz by default STCALIB[25] = 0, use STCLK. STCALIB[24] = 0, exact multiple 10 ms STCALIB[23:0] = 13F, 10 ms/(1/32 KHz) -1 = 319 = 0x13F

TESTBUS_CTRL

Name: TESTBUS_CTRL Register
Description: TESTBUS_CTRL Register
Base Address: 0x4000E000
Offset: 0x38C
Reset Value: 0x00000000

Table 221 TESTBUS_CTRL Register
Bits	Field Name	RW	Reset	Description
31:20	RSVD	R	0x0	Reserved bits
19:17	SEL_PL_LO	RW	0x0	Select testbus pad low bank low bits[07:00]. val \| subsystem 000 \| comm testbus[7:0] 001 \| aon testbus[7:0] 010 \| xf cache testbus[7:0] 011 \| clk testbus[7:0] 100 \| mcu testbus[7:0] 101 \| htable testbus[7:0]
16:14	SEL_PL_HI	RW	0x0	Select testbus pad low bank high bits[15:08]. val \| subsystem 000 \| comm testbus[15:8] 001 \| aon testbus[15:8] 010 \| xf cache testbus[15:8] 011 \| clk testbus[15:8] 100 \| mcu testbus[15:8] 101 \| htable testbus[15:8]
13:11	SEL_PH_LO	RW	0x0	Select testbus pad high bank low bits[23:16]. val \| subsystem 000 \| comm testbus[7:0] 001 \| aon testbus[7:0] 010 \| xf cache testbus[7:0] 011 \| clk testbus[7:0] 100 \| mcu testbus[7:0] 101 \| htable testbus[7:0]
10:8	SEL_PH_HI	RW	0x0	Select testbus pad high bank high bits[31:24]. val \| subsystem 000 \| comm testbus[15:8] 001 \| aon testbus[15:8] 010 \| xf cache testbus[15:8] 011 \| clk testbus[15:8] 100 \| mcu testbus[15:8] 101 \| htable testbus[15:8]
7:5	SEL_LO	RW	0x0	Select MCU testbus low bits[07:00]. val \| ip 00 \| dma testbus[7:0] 01 \| bus_matrix testbus[7:0] 10 \| apb_serial testbus[7:0]
4:2	SEL_HI	RW	0x0	Select MCU testbus high bits[15:08]. val \| ip 00 \| dma testbus[15:8] 01 \| bus_matrix testbus[15:8] 10 \| apb_serial testbus[15:8]
1:0	ORDER	RW	0x0	Testbus order val \| order 00 \| testbus[31:16] = bits[31:28] [27:24] [23:20] [19:16] 01 \| testbus[31:16] = bits[19:16] [31:28] [27:24] [23:20] 10 \| testbus[31:16] = bits[23:20] [19:16] [31:28] [27:24] 11 \| testbus[31:16] = bits[27:24] [23:20] [19:16] [31:28] 00 \| testbus[15:00] = bits[15:12] [11:08] [07:04] [03:00] 01 \| testbus[15:00] = bits[03:00] [15:12] [11:08] [07:04] 10 \| testbus[15:00] = bits[07:04] [03:00] [15:12] [11:08] 11 \| testbus[15:00] = bits[11:08] [07:04] [03:00] [15:12]

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