Features

• Bluetooth LE 5.3 transceiver
  • Supported data rates: 1 Mbps, 2 Mbps, and Long Range (500 kbps, 125 kbps)
  • TX power: Up to 15 dBm
  • RX sensitivity: -99 dBm @ 1 Mbps
  • Power consumption at 3.3 V VBAT input:
    • 6.7 mA TX current @ 0 dBm output power (DC-DC supply, 64 MHz system clock)
    • 87 mA TX current @ 15 dBm output power (SYS_LDO supply, 64 MHz system clock)
    • 5.7 mA RX current @ 1 Mbps (DC-DC supply, 64 MHz system clock)
  • Up to eight simultaneous connections
• Arm^® Cortex^®-M4F 32-bit micro-processor with floating point support:
  • Up to 64 MHz clock frequency
  • Built-in Memory Protection Unit (MPU) supporting eight programmable regions
  • Hardware Floating Point Unit (FPU)
  • Built-in Nested Vectored Interrupt Controller (NVIC)
  • Non-maskable Interrupt (NMI) input
  • Serial Wire Debug (SWD) with 16 breakpoints, two watchpoints, and a debug timestamp counter
  • 39 µA/MHz CoreMark running from Flash @ 3.3 V, 64 MHz from HFRC
• On-chip memory
  • ROM for chip bootloader, system drivers, and Bluetooth LE Protocol Stack code
  • 96 RAM for data and instruction code, with retention capabilities in sleep mode
  • 512 KB Flash for code, system parameter configuration, and user data
• Digital peripherals
  • 1 x general-purpose DMA engine with five channels and 16 handshaking interfaces
• Analog peripherals
  • 1 x 13-bit Sense ADC with a sampling rate of 1 Msps, supporting up to five external I/O channels and three internal signal channels
  • Built-in die temperature and voltage sensors
  • Low-power comparator, supporting wakeup from sleep mode
• Flexible serial peripherals with arbitrary mapping on all digital I/Os
  • 2 x UART modules up to 2 Mbps with flow control and IrDA features, supporting LIN protocol adaption
  • 2 x I2C modules for peripheral communication, up to 1 MHz, operating as either Master or Slave
  • 1 x 8-bit/16-bit/32-bit SPI master interface and 1 x SPI slave interface for host communication
• Security
  • AES 128-bit security module (ECB, CBC)
  • True random number generator (TRNG)
• I/O peripherals
  • 24 multiplexed I/O pins in total
    • Nine general-purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors
    • Eight always-on I/O (AON I/O) pins, supporting wakeup from sleep mode
    • Seven mixed signal I/O (MSIO) pins, configurable to be digital/analog signal interfaces
• Timers
  • 2 x 32-bit general-purpose timers
  • 1 x dual timer with two programmable 32-bit or 16-bit down counters
  • 1 x sleep timer for waking the device up from sleep mode
  • 2 x 3-channel PWMs with edge-aligned mode and center-aligned mode
  • 1 x real-time counter
• Power management
  • On-chip DC-DC/SYS_LDO to provide RF analog voltage and supply CORE_LDO
  • On-chip I/O LDO to provide I/O voltage and supply external components
  • Programmable thresholds for brownout detector (BOD)
  • Supply voltage: 2.3 V−3.6 V
  • I/O voltage: 2.3 V−3.6 V
• Low-power consumption
  • Sleep mode: 3.3 µA (Typical) at 3.3 V VBAT input, with 48 KB SRAM retention on, wakeup sources from AON I/Os, and LFXO_32K running
  • Ultra deep sleep mode: 2.6 µA (Typical), with no memory data in retention and wakeup sources from SLP Timer or AON I/Os
  • OFF mode: 200 nA (Typical), with system in reset mode
• Operating temperature range
  • -40°C to 105°C
• Qualification
  • AEC-Q100 Grade 2
• Packages
  • Wettable flank-plated QFN40: 6.0 x 6.0 x 0.75 mm, 0.5 mm pitch