GR5405 Datasheet | 汇顶科技

DPAD_MUX_00_03

Name: GPIO 00_03 Mux Control Register

Description: This register controls GPIO_0–GPIO_3 mux.

Base Address: 0x4000E900

Offset: 0x00

Reset Value: 0x00002221

Table 232 DPAD_MUX_00_03
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R		Reserved bits
29:24	DPAD_MUX_SEL_03	RW	0x0	Value for GPIO_3 mux
23:22	RSVD	R		Reserved bits
21:16	DPAD_MUX_SEL_02	RW	0x0	Value for GPIO_2 mux
15:14	RSVD	R		Reserved bits
13:8	DPAD_MUX_SEL_01	RW	0x22	Value for GPIO_1 mux
7:6	RSVD	R		Reserved bits
5:0	DPAD_MUX_SEL_00	RW	0x21	Value for GPIO_0 mux

DPAD_MUX_04_07

Name: GPIO 04_07 Mux Control Register

Description: This register controls GPIO_4 and GPIO_6–GPIO_7 mux.

Base Address: 0x4000E900

Offset: 0x04

Reset Value: 0x00000000

Table 233 DPAD_MUX_04_07
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R		Reserved bits
29:24	DPAD_MUX_SEL_07	RW	0x0	Value for GPIO_7 mux
23:22	RSVD	R		Reserved bits
21:16	DPAD_MUX_SEL_06	RW	0x0	Value for GPIO_6 mux
15:6	RSVD	R		Reserved bits
5:0	DPAD_MUX_SEL_04	RW	0x0	Value for GPIO_4 mux

DPAD_MUX_08_09

Name: GPIO 08_09 Mux Control Register

Description: This register controls GPIO_8–GPIO_9 mux.

Base Address: 0x4000E900

Offset: 0x08

Reset Value: 0x00000000

Table 234 DPAD_MUX_08_09
Bits	Field Name	RW	Reset	Description
31:14	RSVD	R		Reserved bits
13:8	DPAD_MUX_SEL_09	RW	0x0	Value for GPIO_9 mux
7:6	RSVD	R		Reserved bits
5:0	DPAD_MUX_SEL_08	RW	0x0	Value for GPIO_8 mux

AON_PAD_MUX_00_03

Name: AON GPIO Pin Mux Control Register

Description: This register controls the AON GPIO pin mux.

Base Address: 0x4000E900

Offset: 0x14

Reset Value: 0x00000000

Table 235 AON_PAD_MUX_00_03
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R		Reserved bits
29:24	AON_PAD_MUX_SEL_03	RW	0x0	Value for AON_GPIO_3 mux
23:22	RSVD	R		Reserved bits
21:16	AON_PAD_MUX_SEL_02	RW	0x0	Value for AON_GPIO_2 mux
15:14	RSVD	R		Reserved bits
13:8	AON_PAD_MUX_SEL_01	RW	0x0	Value for AON_GPIO_1 mux
7:6	RSVD	R		Reserved bits
5:0	AON_PAD_MUX_SEL_00	RW	0x0	Value for AON_GPIO_0 mux

AON_PAD_MUX_04_07

Name: AON GPIO Pin Mux Control Register

Description: This register controls the AON GPIO pin mux.

Base Address: 0x4000E900

Offset: 0x18

Reset Value: 0x00000000

Table 236 AON_PAD_MUX_04_07
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R		Reserved bits
29:24	AON_PAD_MUX_SEL_07	RW	0x0	Value for AON_GPIO_7 mux
23:22	RSVD	R		Reserved bits
21:16	AON_PAD_MUX_SEL_06	RW	0x0	Value for AON_GPIO_6 mux
15:14	RSVD	R		Reserved bits
13:8	AON_PAD_MUX_SEL_05	RW	0x0	Value for AON_GPIO_5 mux
7:6	RSVD	R		Reserved bits
5:0	AON_PAD_MUX_SEL_04	RW	0x0	Value for AON_GPIO_4 mux

MSIO_PAD_MUX_03

Name: MSIO Pin Mux Control Register

Description: This register controls the MSIO_3 pin mux.

Base Address: 0x4000E900

Offset: 0x1C

Reset Value: 0x00000000

Table 237 MSIO_PAD_MUX_03
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R		Reserved bits
29:24	MSIO_A_MUX_SEL_03	RW	0x0	Value for MSIO_3 mux
23:0	RSVD	R		Reserved bits

MSIO_PAD_MUX_04_07

Name: MSIO Pin Mux Control Register

Description: This register controls the MSIO_4–MSIO_7 pin mux.

Base Address: 0x4000E900

Offset: 0x20

Reset Value: 0x00000000

Table 238 MSIO_PAD_MUX_04_07
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R		Reserved bits
29:24	MSIO_A_MUX_SEL_07	RW	0x0	Value for MSIO_7 mux
23:22	RSVD	R		Reserved bits
21:16	MSIO_A_MUX_SEL_06	RW	0x0	Value for MSIO_6 mux
15:14	RSVD	R		Reserved bits
13:8	MSIO_A_MUX_SEL_05	RW	0x0	Value for MSIO_5 mux
7:6	RSVD	R		Reserved bits
5:0	MSIO_A_MUX_SEL_04	RW	0x0	Value for MSIO_4 mux

MSIO_PAD_MUX_08_09

Name: MSIO Pin Mux Control Register

Description: This register controls the MSIO_8–MSIO_9 pin mux.

Base Address: 0x4000E900

Offset: 0x24

Reset Value: 0x00000000

Table 239 MSIO_PAD_MUX_08_09
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R		Reserved bits
13:8	MSIO_A_MUX_SEL_09	RW	0x0	Value for MSIO_9 mux
7:6	RSVD	R		Reserved bits
5:0	MSIO_A_MUX_SEL_08	RW	0x0	Value for MSIO_8 mux

Registers

DPAD_MUX_00_03

DPAD_MUX_04_07

DPAD_MUX_08_09

AON_PAD_MUX_00_03

AON_PAD_MUX_04_07

MSIO_PAD_MUX_03

MSIO_PAD_MUX_04_07

MSIO_PAD_MUX_08_09

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