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GR551x Datasheet

版本：

Rev.2.6

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文档中心 > GR551x Datasheet/ Peripherals / Sense Analog-to-Digital Converter (SADC)/ Registers Copy URL

Registers

FIFO_RD

Name: Sense ADC FIFO Register
Description: Reading this register will pop an entry from the sense ADC FIFO.
Base Address: 0xA000E000
Offset: 0x00
Reset Value: 0x00000000

表 213 Sense ADC FIFO Register
Bits	Field Name	RW	Reset	Description
31:0	DATA	R	0x0	When the register is read, data in the FIFO buffer is accessed.

FIFO_THD

Name: Sense ADC FIFO Threshold Register
Description: This register is used to set the threshold at which the DMA request is made to the hardware handshake mechanism.
Base Address: 0xA000E000
Offset: 0x100
Reset Value: 0x00000000

表 214 Sense ADC FIFO Threshold Register
Bits	Field Name	RW	Reset	Description
31:6	RSVD	R		Reserved bits
5:0	THD	RW	0x0	This is used to set the threshold at which the DMA request is made to the hardware handshake mechanism.

FIFO_STAT

Name: Sense ADC Status Register
Description: This register contains the number of valid data entries in the ADC FIFO memory.
Base Address: 0xA000E000
Offset: 0x104
Reset Value: 0x00000000

表 215 Sense ADC Status Register
Bits	Field Name	RW	Reset	Description
31:9	RSVD	R		Reserved bits
8	VAL	R	0x0	Identify whether FIFO is empty Value: 0x0: FIFO is empty 0x1: FIFO is not empty
7	RSVD	R		Reserved bits
6:0	COUNT	R	0x0	Sense ADC FIFO Count, number of 32-bit words in the FIFO. Maximum value is 0x40 or decimal 64.

CFG

Name: Sense ADC Configuration Register
Description: This register is used to configure reference, channels and input mode of ADC.
Base Address: 0xA000C500
Offset: 0x08
Reset Value: 0x0708070A

表 216 Sense ADC Configuration Register
Bits	Field Name	RW	Reset	Description
31	RST	RW	0x0	Reset ADC Value: 0x0: None 0x1: Reset
30	EN	RW	0x0	Enable ADC Value: 0x0: Disable ADC 0x1: Enable ADC
29:27	REF_SEL	RW	0x0	Reference Voltage Select Value: 0x0: Buffered internal reference 0x1: Reserved 0x2: Reserved 0x3: Using MSIO0 as a reference 0x4: Using MSIO1 as a reference 0x5: Using MSIO2 as a reference 0x6: Using MSIO3 as a reference 0x7: Reserved Note: Because the maximum input for any MSIO is supposed to be VBATT. So in this case, there is no benefit from using an external input higher than VBATT/2.
26:24	REF_HP_MODE	RW	0x7	Used to define current in the reference circuit :Default-<0x0> at 100 Ksps and <0x7> at 1 Msps
23:22	Reserved	R		Reserved bits
21:19	CH_P	RW	0x1	Used to define input for channel P Value: 0x0: MSIO0 as input 0x1: MSIO1 as input 0x2: MSIO2 as input 0x3: MSIO3 as input 0x4: MSIO4 as input
18:16	CH_N	RW	0x0	Used to define input for channel N Value: 0x0: MSIO0 as input 0x1: MSIO1 as input 0x2: MSIO2 as input 0x3: MSIO3 as input 0x4: MSIO4 as input 0x5: Temperature sensor as input 0x6: Battery sensor as input 0x7: Internal reference as input
15	EN_TMP	RW	0x0	Enable temperature sensor Value: 0x0: Disable 0x1: Enable
14	EN_VBAT	RW	0x0	Enable battery sensor Value: 0x0: Disable 0x1: Enable
13	MODE	RW	0x0	Used to define operation either single ended or differential. Value: 0x0: Differential 0x1: Single ended
12	EN_CAL	RW	0x0	Used to swap inputs of comparator for offset calibration. Value: 0x0: Disable 0x1: Enable
11	RSVD	R		Reserved bits
10:8	CODE_IN	RW	0x7	Used to define dynamic range of ADC. Default set to <0x7>, for higher input signal frequencies close to Nyquist rate use <0x1>
7:4	RSVD	R		Reserved bits
3:0	BIAS_RES_CTRL	RW	0xA	Buffered internal reference Value: 0x3: 0.85 V 0x7: 1.28 V 0xA: 1.6 V Note: For any specific reference value (Vref), the maximum ADC input is supposed to be 2 x Vref.

CLK

Name: Sense ADC Clock Register
Description: This register selects ADC clock.
Base Address: 0xA000C500
Offset: 0x40
Reset Value: 0x00000000

表 217 Sense ADC Clock Register
Bits	Field Name	RW	Reset	Description
31	CLK_EN	RW	0x0	Enable ADC clock Value: 0x0: Disable 0x1: Enable
30:28	CLK_SEL	RW	0x0	ADC clock select Value: 0x0: 16 MHz 0x1: 8 MHz 0x2: 4 MHz 0x3: 2 MHz 0x4: 1.6 MHz 0x5: 1 MHz
27:0	RSVD	R		Reserved bits

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