Functional Description

XQSPI block assists the MCU with fast boot up and code execution. It consists of a Flash cache controller and a QSPI XIP Flash controller which is capable of XIP reads from external NOR Flash devices during cache misses. XIP is a way that allows an AHB master (in this case, the MCU) to directly read the contents of Flash devices simply by reading from the address space of the XQSPI controller. During XIP read, cache line is also refilled at Least Frequently Used (LFU) location to reduce future chance of cache miss. The block top level contains three major interfaces:

XQSPI supports common industry-standard QSPI FLASH devices: Winbond W25Q, Micron N25Q, Spansion S25FL, and Macronix MX25L in addition to GD25VQ and GD25LQ families, as well as Gigadevice and PUYA devices.

When XIP is enabled, QSPI can do normal read, fast read, fast read dual out, fast read quad out, fast read dual I/O and fast read quad I/O through AHB bus read transactions. This is code execution path from Flash memory. Cache can greatly reduce the read latency if the code snippet can be found in the cache tag memory, thus improving the performance.

With XIP disabled, CPU can erase and program the FLASH memory through APB bus. This is usually done one-time only or in code maintenance phase and patching.