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GR551x Datasheet

版本：

Rev.2.6

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文档中心 > GR551x Datasheet/ Peripherals / PWM/ Registers Copy URL

Registers

MODE

Name: Mode Register
Description: This register sets PWM operation mode
Base Address: 0xA000C900 + x*0x300
Offset: 0x0
Reset Value: 0x00000000

Note:

x* is used to identify which PWM Module is x⁰, or x¹.

表 297 Mode Register
Bits	Field Name	RW	Reset	Description
31:6	RSVD	R		Reserved bits
5	PD_C_EN	RW	0x0	PWMC positive-drive mode enable. Value: 0x0: negative-drive mode 0x1: positive-drive mode
4	PD_B_EN	RW	0x0	PWMB positive-drive mode enable. Value: 0x0: negative-drive mode 0x1: positive-drive mode
3	PD_A_EN	RW	0x0	PWMA positive-drive mode enable. Value: 0x0: negative-drive mode 0x1: positive-drive mode
2	BREATH_EN	RW	0x0	Breath mode enable. Value: 0x0: flicker mode 0x1: breath mode
1	PAUSE	RW	0x0	PWM pause signal. Value: 0x0: Ongoing 0x1: Pause
0	EN	RW	0x0	Enable PWM. Value: 0x0: Disable 0x1: Enable

UPDATE

Name: Update Register
Description: Synchronous update enable register
Base Address: 0xA000C900 + x*0x300
Offset: 0x4
Reset Value: 0x00000000

表 298 Update Register
Bits	Field Name	RW	Reset	Description
30x1:19	RSVD	R		Reserved bits
18	UPDATE_SYNC_SAQCTRL	RW	0x0	Separate update enable of AQCTRL Value: 0x0: Disable 0x1: Enable
17	UPDATE_SYNC_SHOLD	RW	0x0	Separate update enable of HOLD Value: 0x0: Disable 0x1: Enable
16	UPDATE_SYNC_SBRPRD	RW	0x0	Separate update enable of BRPRD Value: 0x0: Disable 0x1: Enable
15	UPDATE_SYNC_SPAUSE	RW	0x0	Separate update enable of PAUSE Value: 0x0: Disable 0x1: Enable
14	UPDATE_SYNC_SCMPC1	RW	0x0	Separate update enable of CMPC1 Value: 0x0: Disable 0x1: Enable
13	UPDATE_SYNC_SCMPC0	RW	0x0	Separate update enable of CMPC0 Value: 0x0: Disable 0x1: Enable
12	UPDATE_SYNC_SCMPB1	RW	0x0	Separate update enable of CMPB1 Value: 0x0: Disable 0x1: Enable
11	UPDATE_SYNC_SCMPB0	RW	0x0	Separate update enable of CMPB0 Value: 0x0: Disable 0x1: Enable
10	UPDATE_SYNC_SCMPA1	RW	0x0	Separate update enable of CMPA1 Value: 0x0: Disable 0x1: Enable
9	UPDATE_SYNC_SCMPA0	RW	0x0	Separate update enable of CMPA0 Value: 0x0: Disable 0x1: Enable
8	UPDATE_SYNC_SPRD	RW	0x0	Separate update enable of PRD Value: 0x0: Disable 0x1: Enable
7:2	RSVD	R		Reserved bits
1	UPDATE_SYNC_AE	RW	0x0	Synchronous update enable Value: 0x0: Disable 0x1: Enable
0	UPDATE_SYNC_AG	R	0x0	Synchronous update ongoing Value: 0x0: Not ongoing 0x1: Ongoing

PRD

Name: Period Register
Description: This register is used to set the PWM cycle
Base Address: 0xA000C900 + x*0x300
Offset: 0x8
Reset Value: 0x00000000

表 299 Period Register
Bits	Field Name	RW	Reset	Description
31:0	PRD	RW	0x0	The period of PWM output, PRD=f_CLK/f_PWM

CMPA0

Name: Compare A0 Register
Description: Compare register 0 of channel A
Base Address: 0xA000C900 + x*0x300
Offset: 0xC
Reset Value: 0x00000000

表 300 Compare A0 Register
Bits	Field Name	RW	Reset	Description
31:0	CMPA0	RW	0x0	PWMA duty control register0

CMPA1

Name: Compare A1 Register
Description: Compare register 1 of channel A
Base Address: 0xA000C900 + x*0x300
Offset: 0x10
Reset Value: 0x00000000

表 301 Compare A1 Register
Bits	Field Name	RW	Reset	Description
31:0	CMPA1	RW	0x0	PWMA duty control register1

CMPB0

Name: Compare B0 Register
Description: Compare register 0 of channel B
Base Address: 0xA000C900 + x*0x300
Offset: 0x14
Reset Value: 0x00000000

表 302 Compare B0 Register
Bits	Field Name	RW	Reset	Description
31:0	CMPB0	RW	0x0	PWMB duty control register0

CMPB1

Name: Compare B1 Register
Description: Compare register 1 of channel B
Base Address: 0xA000C900 + x*0x300
Offset: 0x18
Reset Value: 0x00000000

表 303 Compare B1 Register
Bits	Field Name	RW	Reset	Description
31:0	CMPB1	RW	0x0	PWMB duty control register1

CMPC0

Name: Compare C0 Register
Description: Compare register 0 of channel C
Base Address: 0xA000C900 + x*0x300
Offset: 0x1C
Reset Value: 0x00000000

表 304 Compare C0 Register
Bits	Field Name	RW	Reset	Description
31:0	CMPC0	RW	0x0	PWMC duty control register0

CMPC1

Name: Compare C1 Register
Description: Compare register 1 of channel C
Base Address: 0xA000C900 + x*0x300
Offset: 0x20
Reset Value: 0x00000000

表 305 Compare C1 Register
Bits	Field Name	RW	Reset	Description
31:0	CMPC1	RW	0x0	PWMC duty control register1

AQCTRL

Name: Action Qualifier Control Register
Description: This register is used to set actions when counter reaches the compare value.
Base Address: 0xA000C900 + x*0x300
Offset: 0x24
Reset Value: 0x00000000

表 306 Action Qualifier Control Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R		Reserved bits
11:10	AQ_CTRL_C1	RW	0x0	Action of event CNT_CMPC1 control register; 0x0: do nothing 0x1: clear 0x2: set 0x3: toggle
9:8	AQ_CTRL_C0	RW	0x0	Action of event CNT_CMPC0 control register; 0x0: do nothing 0x1: clear 0x2: set 0x3: toggle
7:6	AQ_CTRL_B1	RW	0x0	Action of event CNT_CMPB1 control register; 0x0: do nothing 0x1: clear 0x2: set 0x3: toggle
5:4	AQ_CTRL_B0	RW	0x0	Action of event CNT_CMPB0 control register; 0x0: do nothing 0x1: clear 0x2: set 0x3: toggle
3:2	AQ_CTRL_A1	RW	0x0	Action of event CNT_CMPA1 control register; 0x0: do nothing 0x1: clear 0x2: set 0x3: toggle
1:0	AQ_CTRL_A0	RW	0x0	Action of event CNT_CMPA0 control register; 0x0: do nothing 0x1: clear 0x2: set 0x3: toggle

BRPRD

Name: Breath Period Register
Description: This register configures the period of breath mode.
Base Address: 0xA000C900 + x*0x300
Offset: 0x28
Reset Value: 0x00000000

表 307 Breath Period Register
Bits	Field Name	RW	Reset	Description
31:0	BRPRD	RW	0x0	Breath period register, i.e. the required time (number of clock) that the duty changes from 0% to 100% in breath mode.

HOLD

Name: Hold Register
Description: This register configures the hold period on breath mode.
Base Address: 0xA000C900 + x*0x300
Offset: 0x2C
Reset Value: 0x00000000

表 308 Hold Register
Bits	Field Name	RW	Reset	Description
31:24	RSVD	R		Reserved bits
23:0	HOLD	RW	0x0	Breath hold control register. The value should be the required number of clock in breath hold state.

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