Registers
Channel_x_Registers
SRC_ADDR_CHx
- Name: Source Address for Channel x
- Description: The starting source address is programmed by software before the DMA
channel is enabled. While the DMA transfer is in progress, this register is updated to
reflect the source address of the current AHB transfer.Note:
You must program the S_ADDR address to be aligned to CTRL_CHx.SRC_XFE_WIDTH.
- Base Address: 0xA0013000
- Reset Value: 0x0
- Offset: 0x0 + x*0x58
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:32 |
RSVD |
R |
Reserved field |
|
|
31:0 |
SRC_ADDR |
RW |
0x0 |
Current Source Address of DMA transfer. Updated after each source transfer. The SRC_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true |
DEST_ADDR_CHx
- Name: Destination Address Register for Channel x
- Description: The starting destination address is programmed by software before the
DMA channel is enabled. While the DMA transfer is in progress, this register is updated to
reflect the destination address of the current AHB transfer.Note:
You must program the DEST_ADDR_CH to be aligned to CTRL_CHx.DEST_XFE_WIDTH.
- Base Address: 0xA0013000
- Offset: 0x8 + x*0x58
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:32 |
RSVD |
R |
Reserved field |
|
|
31:0 |
DEST_ADDR |
RW |
0x0 |
Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true |
CTRL_CHx
- Name: Control Register for Channel x
- Description: This register contains fields that control the DMA transfer.Note:
You need to program this register prior to enabling the channel.
- Base Address: 0xA0013000
- Offset: 0x18 + x*0x58
- Reset Value: 0x0000000200304801
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:45 |
RSVD |
R |
0x0 |
Reserved field Volatile: true |
|
44 |
DONE |
RW |
0x0 |
Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx[63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is completed. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize = 2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. Volatile: true |
|
43:32 |
BLOCK_XFE_SIZE |
RW |
0x2 |
Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_XFE_SIZE indicates the total number of single transactions to perform for every block transfer; a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_XFE_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what the flow controller is. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true |
|
31:23 |
Rsvd_1_CTRL |
R |
0x0 |
Reserved field Volatile: true |
|
22:20 |
XFE_TYPE_FC |
RW |
0x3 |
Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. Value:
Volatile: true |
|
19:17 |
Rsvd_CTRL |
R |
0x0 |
Reserved field Volatile: true |
|
16:14 |
SRC_MSIZE |
RW |
0x1 |
Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_XFE_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. Note: This value is not related to the AHB bus master HBURST bus. Value:
Volatile: true |
|
13:11 |
DEST_MSIZE |
RW |
0x1 |
Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_XFE_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Note: This value is not related to the AHB bus master HBURST bus. Value:
Volatile: true |
|
10:9 |
SRC_ADDR_INC |
RW |
0x0 |
Source Address Increment. Indicate whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to "No change". Value:
Volatile: true |
|
8:7 |
DEST_ADDR_INC |
RW |
0x0 |
Destination Address Increment. Indicate whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to \"No Change\". Value:
Volatile: true |
|
6:4 |
SRC_XFE_WIDTH |
RW |
0x0 |
Source Transfer Width. Mapped to AHB bus Hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. Value:
Volatile: true |
|
3:1 |
DEST_XFE_WIDTH |
RW |
0x0 |
Destination Transfer Width. Mapped to AHB bus Hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. Value:
Volatile: true |
|
0 |
INT_EN |
RW |
0x1 |
Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw* interrupt registers still assert if CTRL_CHx.INT_EN = 0. Value:
Volatile: true |
CFG_CHx
- Name: Configuration Register for Channel x
- Description: This register contains fields that configure the DMA transfer. The
channel configuration register remains fixed for all blocks of a multi-block transfer.Note:
You need to program this register prior to enabling the channel.
- Base Address: 0xA0013000
- Offset: 0x40 + x*0x58
- Reset Value: 0x0000000400000e00 + (x*0x20)
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:47 |
RSVD |
R |
Reserved field |
|
|
46:43 |
DEST_PER |
RW |
0x0 |
Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFG_CHx.HSG_SEL_DEST field is 0; otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. Note: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. |
|
42:39 |
SRC_PER |
RW |
0x0 |
Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. Note: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. |
|
38:37 |
RSVD |
R |
Reserved field |
|
|
36:34 |
PROT_CTRL |
RW |
0x0 |
Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows:
|
|
33 |
FIFO_MODE |
RW |
0x0 |
FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. Value:
|
|
32 |
FLOW_CTRL_MODE |
RW |
0x0 |
Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. Value:
|
|
31 |
RELOAD_DEST |
RW |
0x0 |
Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. Value:
|
|
30 |
RELOAD_SRC |
RW |
0x0 |
Automatic Source Reload. The SRC_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. Value:
|
|
29:20 |
Rsvd_CFG |
R |
0x0 |
Reserved field |
|
19 |
SRC_HSG_POL |
RW |
0x0 |
Source Handshaking Interface Polarity. Value:
|
|
18 |
DEST_HSG_POL |
RW |
0x0 |
Destination Handshaking Interface Polarity. Value:
|
|
17:12 |
Rsvd_CFG |
R |
0x0 |
Reserved field |
|
11 |
HSG_SEL_SRC |
RW |
0x0 |
Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for source requests on this channel. If the source peripheral is memory, then this bit is ignored. Value:
|
|
10 |
HSG_SEL_DEST |
RW |
0x0 |
Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. Value:
|
|
9 |
FIFO_EMPTY |
R |
0x0 |
Channel FIFO status. Indicate if there is data left in the channel FIFO. It can be used in conjunction with CFG_CHx to cleanly disable a channel. Value:
|
|
8 |
CH_SUSP |
RW |
0x0 |
Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. It can also be used in conjunction with CFG_CHx to cleanly disable a channel without losing any data. Value:
|
|
7:5 |
CH_PRIOR |
RW |
Channel Priority. A priority of 7 is the highest priority and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. Value:
|
|
|
4:0 |
RSVD |
R |
Reserved field |
Interrupt_Registers
INT_RSTAT_TC
- Name: Raw Status for Transfer Complete Interrupt
- Description: Interrupt events are stored in this Raw Interrupt Status register before masking. This register has a bit allocated to per channel; for example, INT_RSTAT_TC[2] is the Channel 2 raw transfer complete interrupt.
- Each bit in
this register is cleared by writing a 1 to the corresponding location in the INT_CLR_TC register.Note:
Write access is available to this register or software for testing purposes only. Under normal operation, writes to this register are not recommended.
- Base Address: 0xA0013000
- Offset: 0x2c0
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
Rsvd_INT_RSTAT_TC |
R |
0x0 |
Reserved field |
|
7:0 |
RAW |
RW |
0x0 |
Raw Status for Transfer Complete Interrupt Value:
|
INT_RSTAT_BTC
- Name: Raw Status for Block Transfer Complete Interrupt
- Description: Interrupt events are stored in this Raw Interrupt Status register
before masking. This register has a bit allocated to per channel; for example,
INT_RSTAT_BTC[2] is the Channel 2 raw block complete interrupt.
Each bit in this register is cleared by writing a 1 to the corresponding location in the CLR_BLK register.
Note:Write access is available to this register or software for testing purposes only. Under normal operation, writes to this register are not recommended.
- Base Address: 0xA0013000
- Offset: 0x2c8
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_RSTAT_BTC |
R |
0x0 |
Reserved field |
|
7:0 |
RAW |
RW |
0x0 |
Raw Status for Block Transfer Complete Interrupt Value:
|
INT_RSTAT_STC
- Name: Raw Status for Source Transaction Complete Interrupt
- Description: Interrupt events are stored in this Raw Interrupt Status register before masking. This register has a bit allocated per channel; for example, INT_RSTAT_STC[2] is the Channel 2 raw source transaction complete interrupt.
- Each bit in
this register is cleared by writing a 1 to the corresponding location in the INT_CLR_STC register.Note:
Write access is available to this register or software testing purposes only. Under normal operation, writes to this register are not recommended.
- Base Address: 0xA0013000
- Offset: 0x2D0
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_RSTAT_STC |
R |
0x0 |
Reserved field |
|
7:0 |
RAW |
RW |
0x0 |
Raw Status for Source Transaction Complete Interrupt Value:
|
INT_RSTAT_DTC
- Name: Raw Status for Destination Transaction Complete Interrupt
- Description: Interrupt events are stored in this Raw Interrupt Status register
before masking. This register has a bit allocated per channel; for example, INT_RSTAT_DTC[2]
is the Channel 2 raw destination transaction complete interrupt.
Each bit in this register is cleared by writing a 1 to the corresponding location in the INT_CLR_DTC register.
Note:Write access is available to this register or software testing purposes only. Under normal operation, writes to this register are not recommended.
- Base Address: 0xA0013000
- Offset: 0x2d8
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_RSTAT_DTC |
R |
0x0 |
Reserved field |
|
7:0 |
RAW |
RW |
0x0 |
Raw Status for Destination Transaction Complete Interrupt Value:
|
INT_RSTAT_ERR
- Name: Raw Status for Error Interrupt
- Description: Interrupt events are stored in this Raw Interrupt Status register
before masking. This register has a bit allocated per channel; for example, INT_RSTAT_ERR[2]
is the Channel 2 raw error interrupt.
Each bit in this register is cleared by writing a 1 to the corresponding location in the INT_CLR_ERR register.
Note:Write access is available to this register or software testing purposes only. Under normal operation, writes to this register are not recommended.
- Base Address: 0xA0013000
- Offset: 0x2E0
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_RSTAT_ERR |
R |
0x0 |
Reserved field |
|
7:0 |
RAW |
RW |
0x0 |
Raw Status for Error Interrupt Value:
|
INT_STAT_TC
- Name: Status for Transfer Complete Interrupt
- Description: Channel DMA Transfer complete interrupt event from all channels is stored in this Interrupt Status register after masking. This register has a bit allocated per channel; for example, INT_STAT_TC [2] is the Channel 2 source DMA transfer complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
- Base Address: 0xA0013000
- Offset: 0x2E8
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_STAT_TC |
R |
0x0 |
Reserved field |
|
7:0 |
STAT |
R |
0x0 |
Status for Transfer Complete Interrupt Value:
|
INT_STAT_BTC
- Name: Status for Block Transfer Complete Interrupt
- Description: Channel Block complete interrupt event from all channels is stored in this Interrupt Status register after masking. This register has a bit allocated per channel; for example, INT_STAT_BTC[2] is the Channel 2 block complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
- Base Address: 0xA0013000
- Offset: 0x2F0
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_STAT_BTC |
R |
0x0 |
Reserved field |
|
7:0 |
STAT |
R |
0x0 |
Status for Block Transfer Complete Interrupt Value:
|
INT_STAT_STC
- Name: Status for Source Transaction Complete Interrupt
- Description: Channel Source Transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. This register has a bit allocated per channel; for example, INT_STAT_STC[2] is the Channel 2 source transaction complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
- Base Address: 0xA0013000
- Offset: 0x2F8
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_STAT_STC |
R |
0x0 |
Reserved field |
|
7:0 |
STAT |
R |
0x0 |
Status for Source Transaction Complete Interrupt Value:
|
INT_STAT_DTC
- Name: Status for Destination Transaction Complete Interrupt
- Description: Channel destination transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. This register has a bit allocated per channel; for example, INT_STAT_DTC[2] is the Channel 2 status destination transaction complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
- Base Address: 0xA0013000
- Offset: 0x300
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_STAT_DTC |
R |
0x0 |
Reserved field |
|
7:0 |
STAT |
R |
0x0 |
Status for Destination Transaction Complete Interrupt Value:
|
INT_STAT_ERR
- Name: Status for Error Interrupt
- Description: Channel Error interrupt event from all channels is stored in this Interrupt Status register after masking. This register has a bit allocated per channel; for example, INT_STAT_ERR[2] is the Channel 2 status Error interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
- Base Address: 0xA0013000
- Offset: 0x308
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_STAT_ERR |
R |
0x0 |
Reserved field |
|
7:0 |
STAT |
R |
0x0 |
Status for Error Interrupt Value:
|
INT_MASK_TC
- Name: MASK for Transfer Complete Interrupt
- Description: The contents of the Raw Status register INT_RSTAT_TC is masked with
the contents of the Mask register INT_MASK_TC. Each bit of register is allocated per
channel; for example, INT_MASK_TC[2] is the mask bit for the Channel 2 transfer complete
interrupt.
A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the INT_MASK_TC register writes a 1 into INT_MASK_TC[0], while INT_MASK_TC[7:1] remains unchanged. Writing hex 00xx leaves INT_MASK_TC[7:0] unchanged.
Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the Status registers and int_* port signals.
- Base Address: 0xA0013000
- Offset: 0x310
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
RSVD_INT_MASK_TC |
R |
0x0 |
Reserved field |
|
15:8 |
INT_MASK_WE |
W |
0x0 |
Interrupt Mask Write Enable Value:
|
|
7:0 |
INT_MASK |
RW |
0x0 |
Mask for Transfer Complete Interrupt Value:
|
INT_MASK_BTC
- Name: Mask for Block Transfer Complete Interrupt
- Description: The contents of the Raw Status register INT_RSTAT_BTC is masked with
the contents of the Mask register INT_MASK_BTC. Each bit of register is allocated per
channel; for example, INT_MASK_BTC[2] is the mask bit for the Channel 2 block complete
interrupt.
A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the INT_MASK_BTC register writes a 1 into INT_MASK_BTC[0], while INT_MASK_BTC[7:1] remains unchanged. Writing hex 00xx leaves INT_MASK_BTC[7:0] unchanged.
Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the Status registers and int_* port signals.
- Base Address: 0xA0013000
- Offset: 0x318
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
RSVD_INT_MASK_BTC |
R |
0x0 |
Reserved field |
|
15:8 |
INT_MASK_WE |
W |
0x0 |
Interrupt Mask Write Enable Value:
|
|
7:0 |
INT_MASK |
RW |
0x0 |
Mask for Block Transfer Complete Interrupt Value:
|
INT_MASK_STC
- Name: MASK for Source Transaction Complete Interrupt
- Description: The contents of the Raw Status register INT_RSTAT_STC is masked with
the contents of the Mask register INT_MASK_STC. Each bit of register is allocated per
channel; for example, INT_MASK_STC[2] is the mask bit for the Channel 2 source transaction
complete interrupt.
When the source peripheral of DMA channel i is memory, then the source transaction complete interrupt, INT_MASK_STC[i], must be masked to prevent an erroneous triggering of an interrupt on the int_combined signal.
A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, write hex 01x1 to the INT_MASK_STC register and write a 1 into INT_MASK_STC[0], while INT_MASK_STC[7:1] remains unchanged. Writing hex 00xx leaves INT_MASK_STC[7:0] unchanged.
Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the Status registers and int_* port signals.
- Base Address: 0xA0013000
- Offset: 0x320
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
RSVD_INT_MASK_STC |
R |
0x0 |
Reserved field |
|
15:8 |
INT_MASK_WE |
W |
0x0 |
Interrupt Mask Write Enable Value:
|
|
7:0 |
INT_MASK |
RW |
0x0 |
Mask for Source Transaction Complete Interrupt Value:
|
INT_MASK_DTC
- Name: Mask for Destination Transaction Complete Interrupt
- Description: The contents of the Raw Status register INT_RSTAT_DTC is masked with
the contents of the Mask register INT_MASK_DTC. Each bit of register is allocated per
channel; for example, INT_MASK_DTC[2] is the mask bit for the Channel 2 destination
transaction complete interrupt.
When the destination peripheral of DMA channel i is memory, then the destination transaction complete interrupt, INT_MASK_DTC[i], must be masked to prevent an erroneous triggering of an interrupt on the int_combined(_n) signal.
A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the INT_MASK_DTC register writes a 1 into INT_MASK_DTC[0], while INT_MASK_DTC[7:1] remains unchanged. Writing hex 00xx leaves INT_MASK_DTC[7:0] unchanged.
Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the Status registers and int_* port signals.
- Base Address: 0xA0013000
- Offset: 0x328
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
RSVD_INT_MASK_DTC |
R |
0x0 |
Reserved field |
|
15:8 |
INT_MASK_WE |
W |
0x0 |
Interrupt Mask Write Enable Value:
|
|
7:0 |
INT_MASK |
RW |
0x0 |
Mask for Destination Transaction Complete Interrupt Value:
|
INT_MASK_ERR
- Name: Mask for Error Interrupt
- Description: The contents of the Raw Status register INT_RSTAT_ERR is masked with
the contents of the Mask register INT_MASK_ERR. Each bit of register is allocated per
channel; for example, INT_MASK_ERR[2] is the mask bit for the Channel 2 error interrupt.
A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the INT_MASK_ERR register writes a 1 into INT_MASK_ERR[0], while INT_MASK_ERR[7:1] remains unchanged. Writing hex 00xx leaves INT_MASK_ERR[7:0] unchanged.
Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the Status registers and int_* port signals.
- Base Address: 0xA0013000
- Offset: 0x330
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
RSVD_INT_MASK_ERR |
R |
0x0 |
Reserved field |
|
15:8 |
INT_MASK_WE |
W |
0x0 |
Interrupt Mask Write Enable Value:
|
|
7:0 |
INT_MASK |
RW |
0x0 |
Mask for Error Interrupt Value:
|
INT_CLR_TC
- Name: Clear for Transfer Complete Interrupt
- Description: Each bit in the INT_RSTAT_TC and INT_STAT_TC is cleared on the same cycle by writing a 1 to the corresponding location in the registers. Each bit is allocated per channel; for example, INT_CLR_TC[2] is the clear bit for the Channel 2 transfer done interrupt. Writing a 0 has no effect. This registers are not readable.
- Base Address: 0xA0013000
- Offset: 0x338
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_CLR_TC |
W |
0x0 |
Reserved field |
|
7:0 |
CLR |
W |
0x0 |
Clear for Transfer Complete Interrupt Value:
|
INT_CLR_BTC
- Name: Clear for Block Transfer Complete Interrupt
- Description: Each bit in the INT_RSTAT_BTC and INT_STAT_BTC is cleared on the same cycle by writing a 1 to the corresponding location in the registers. Each bit is allocated per channel; for example, INT_CLR_BTC[2] is the clear bit for the Channel 2 block done interrupt. Writing a 0 has no effect. These registers are not readable.
- Base Address: 0xA0013000
- Offset: 0x340
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_CLR_BTC |
W |
0x0 |
Reserved field |
|
7:0 |
CLR |
W |
0x0 |
Clear for Block Transfer Complete Interrupt |
INT_CLR_STC
- Name: Clear for Source Transaction Complete Interrupt
- Description: Each bit in the INT_RSTAT_STC and INT_STAT_STC is cleared on the same cycle by writing a 1 to the corresponding location in the registers. Each bit is allocated per channel; for example, INT_CLR_STC[2] is the clear bit for the Channel 2 source transaction done interrupt. Writing a 0 has no effect. This registers are not readable.
- Base Address: 0xA0013000
- Offset: 0x348
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_CLR_STC |
W |
0x0 |
Reserved field |
|
7:0 |
CLR |
W |
0x0 |
Clear for Source Transaction Complete Interrupt Value:
|
INT_CLR_DTC
- Name: Clear for Destination Transaction Complete Interrupt
- Description: Each bit in the INT_RSTAT_DTC and INT_STAT_DTC is cleared on the same cycle by writing a 1 to the corresponding location in the registers. Each bit is allocated per channel; for example, INT_CLR_DTC[2] is the clear bit for the Channel 2 destination transaction done interrupt. Writing a 0 has no effect. This registers are not readable.
- Base Address: 0xA0013000
- Offset: 0x350
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_CLR_DTC |
W |
0x0 |
Reserved field |
|
7:0 |
CLR |
W |
0x0 |
Clear for Destination Transaction Complete Interrupt Value:
|
INT_CLR_ERR
- Name: Clear for Error Interrupt
- Description: Each bit in the INT_RSTAT_ERR and INT_STAT_ERR is cleared on the same cycle by writing a 1 to the corresponding location in the registers. Each bit is allocated per channel; for example, INT_CLR_ERR[2] is the clear bit for the Channel 2 error interrupt. Writing a 0 has no effect. This registers are not readable.
- Base Address: 0xA0013000
- Offset: 0x358
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:8 |
RSVD_INT_CLR_ERR |
W |
0x0 |
Reserved field |
|
7:0 |
CLR |
W |
0x0 |
Clear for Error Interrupt Value:
|
INT_STAT_ET
- Name: Status for each Interrupt type
- Description: The contents of each of the five Status registers INT_STAT_TC, INT_STAT_BTC, INT_STAT_STC, INT_STAT_DTC, INT_STAT_ERR are ORed to produce a single bit for each interrupt type in the Combined Status register (INT_STAT_ET). This register is read-only.
- Base Address: 0xA0013000
- Offset: 0x360
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:5 |
RSVD_INT_STAT_ET |
R |
0x0 |
Reserved field |
|
4 |
ERR |
R |
0x0 |
OR of the contents of INT_STAT_ERR Value:
|
|
3 |
DEST_XFE_CPLT |
R |
0x0 |
OR of the contents of INT_STAT_DTC Value:
|
|
2 |
SRC_XFE_CPLT |
R |
0x0 |
OR of the contents of INT_STAT_STC Value:
|
|
1 |
BLK_XFE_CPLT |
R |
0x0 |
OR of the contents of INT_STAT_BTC register Value:
|
|
0 |
XFE_CPLT |
R |
0x0 |
OR of the contents of INT_STAT_TC register Value:
|
Software_Handshake_Registers
REQ_SST
- Name: Source Software Transaction Request register
- Description: A bit is assigned for each channel in this register. REQ_SST[n] is
ignored when software handshaking is not enabled for the source of channel n.
A channel SRC_REQ bit is written only if the corresponding channel write enable bit in the SRC_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register. For example, writing hex 0101 writes a 1 into REQ_SST[0], while REQ_SST[7:1] remains unchanged. Writing hex 00xx leaves REQ_SST[7:0] unchanged. This allows software to set a bit in the REQ_SST register without performing a read-modified write operation.
- Base Address: 0xA0013000
- Offset: 0x368
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
Rsvd_1_REQ_SST |
R |
0x0 |
Reserved field |
|
15:8 |
SRC_REQ_WE |
RW |
0x0 |
Source Software Transaction Request write enable Value:
|
|
7:0 |
SRC_REQ |
RW |
0x0 |
Source Software Transaction Request Value:
|
REQ_DST
- Name: Destination Software Transaction Request Register
- Description: A bit is assigned for each channel in this register. REQ_DST[n] is
ignored when software handshaking is not enabled for the source of channel n.
A channel DEST bit is written only if the corresponding channel write enable bit in the DEST_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
- Base Address: 0xA0013000
- Offset: 0x370
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
Rsvd_1_REQ_DST |
R |
0x0 |
Reserved field |
|
15:8 |
DEST_REQ_WE |
RW |
0x0 |
Destination Software Transaction Request write enable Value:
|
|
7:0 |
DEST_REQ |
RW |
0x0 |
Destination Software Transaction Request Value:
|
REQ_SGL_ST
- Name: Source Single Transaction Request Register
- Description: A bit is assigned for each channel in this register. REQ_SGL_ST is
ignored when software handshaking is not enabled for the source of channel n.
A channel SRC_SGL_REQ bit is written only if the corresponding channel write enable bit in the SRC_SGL_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
- Base Address: 0xA0013000
- Offset: 0x378
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
Rsvd_1_REQ_SGL_ST |
R |
0x0 |
Reserved field |
|
15:8 |
SRC_SGL_REQ_WE |
RW |
0x0 |
Source Single Transaction Request write enable Value:
|
|
7:0 |
SRC_SGL_REQ |
RW |
0x0 |
Source Single Transaction Request Value:
|
REQ_SGL_DT
- Name: Destination Single Transaction Request Register
- Description: A bit is assigned for each channel in this register. REQ_SGL_DT is
ignored when software handshaking is not enabled for the destination of channel n.
A channel DEST_SGL_REQ bit is written only if the corresponding channel write enable bit in the DST_SGL_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
- Base Address: 0xA0013000
- Offset: 0x380
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
Rsvd_1_REQ_SGL_DT |
R |
0x0 |
Reserved field |
|
11:8 |
DST_SGL_REQ_WE |
RW |
0x0 |
Destination Single Transaction Request write enable Value:
|
|
7:0 |
DEST_SGL_REQ |
RW |
0x0 |
Destination Single Transaction Request Value:
|
REQ_LST_ST
- Name: Source Last Transaction Request Register
- Description: A bit is assigned for each channel in this register. REQ_LST_ST is
ignored when software handshaking is not enabled for the source of channel n, or when the
source of channel n is not a flow controller.
A channel LST_SRC bit is written only if the corresponding channel write enable bit in the LST_SRC_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
- Base Address: 0xA0013000
- Offset: 0x388
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
Rsvd_1_REQ_LST_ST |
R |
0x0 |
Reserved field |
|
15:8 |
LST_SRC_WE |
RW |
0x0 |
Source Last Transaction Request write enable Value:
|
|
7:0 |
LST_SRC |
RW |
0x0 |
Source Last Transaction Request register Value:
|
REQ_LST_DT
- Name: Destination Last Transaction Request Register
- Description: A bit is assigned for each channel in this register. REQ_LST_DT is
ignored when software handshaking is not enabled for the destination of channel n or when
the destination of channel n is not a flow controller.
A channel LST_DEST bit is written only if the corresponding channel write enable bit in the LST_DEST_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
- Base Address: 0xA0013000
- Offset: 0x390
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
Rsvd_1_REQ_LST_DT |
R |
0x0 |
Reserved field |
|
15:8 |
LST_DEST_WE |
RW |
0x0 |
Destination Last Transaction Request write enable Value:
|
|
7:0 |
LST_DEST |
RW |
0x0 |
Destination Last Transaction Request Value:
|
Miscellaneous_Registers
CFG
- Name: DMA Configuration Register
- Description: This register is used to enable the DMA, which must be done before
any channel activity can begin.
If the global channel enable bit is cleared while any channel is still active, then CFG.DMA_EN still returns 1 to indicate that there are channels still active until hardware has terminated all activity on all channels, at which point the CFG.DMA_EN bit returns 0.
- Base Address: 0xA0013000
- Offset: 0x398
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:1 |
RSVD_CFG |
R |
0x0 |
Reserved field |
|
0 |
DMA_EN |
RW |
0x0 |
DMA Enable bit. Value:
|
CH_EN
- Name: DMA Channel Enable Register
- Description: This is the DMA Channel Enable Register. If software needs to set up
a new channel, then it can read this register in order to find out which channels are
currently inactive; it can then enable an inactive channel with the required priority.
All bits of this register are cleared to 0 when the global DMA channel enable bit, CFG[0], is 0. When the global channel enable bit is 0, then a write to the CH_EN register is ignored and a read will always read back 0.
The channel enable bit, CH_EN.CH_EN, is written only if the corresponding channel write enable bit, CH_EN.CH_EN_WE, is asserted on the same AHB write transfer. For example, writing hex 01x1 writes a 1 into CH_EN[0], while CH_EN[7:1] remains unchanged. Writing hex 00xx leaves CH_EN[7:0] unchanged. Note that a read-modified write is not required.
- Base Address: 0xA0013000
- Offset: 0x3a0
- Reset Value: 0x0
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
|
63:16 |
Rsvd_1_CH_EN |
R |
0x0 |
Reserved field |
|
15:8 |
CH_EN_WE |
W |
0x0 |
Channel enable register |
|
7:0 |
CH_EN |
RW |
0x0 |
Channel Enable. The CH_EN.CH_EN bit is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer. Value:
|
