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文档中心 > GR551x Datasheet/ Peripherals / GPIO/ Registers Copy URL

Registers

DPAD_RE_N

  • Name: GPIO pull up/down resistor enable register
  • Description: This register decides whether to use a pull up/down resistor.
  • Base Address: 0xA000E000
  • Offset: 0x208
  • Reset Value: 0x00000000
表 49 DPAD_RE_N
Bits Field Name RW Reset Description
31:0 DPAD_RE_N RW 0x0

Enable a pull up/down resistor to the RETENTION PAD.

Value:
  • 0x0: Enable resistor inputs to pad (GPIO_0 - GPIO_31)
  • 0x1: Disable resistor inputs to pad (GPIO_0 - GPIO_31)

DPAD_RTYPE

  • Name: GPIO pull resistor type control register
  • Description: This register chooses the pull resistor type.
  • Base Address: 0xA000E000
  • Offset: 0x210
  • Reset Value: 0x00000000
表 50 DPAD_RTYPE
Bits Field Name RW Reset Description
31:0 DPAD_RTYPE RW 0x0

Resistor type inputs to the RETENTION PAD.

Value:
  • 0x0: Pull down (when DPAD_RE_N = 0)
  • 0x1: Pull up (when DPAD_RE_N = 0)

GPIOx_DATA

  • Name: GPIO data value register
  • Description: This register contains the input data and can write data output register.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x0000
  • Reset Value:0x00000000
表 51 GPIO data value register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 DATA RW 0x0

Data value [15:0]

Read: The input level state(high or low) at pin

Write: To data output register

GPIOx_DATA_OUT

  • Name: GPIO data output register
  • Description: This register contains the output data.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x0004
  • Reset Value:0x00000000
表 52 GPIO data output register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 DATA_OUT RW 0x0

Data output register value [15:0]

Read: Current value of data output register

Write: To data output register

GPIOx_OUT_EN

  • Name: GPIO output enable register
  • Description: This register is used to enable output.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x0010
  • Reset Value: 0x00000000
表 53 GPIO output enable register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 EN RW 0x0

Output enable set [15:0]

Read:

  • 0x0: As input
  • 0x1: As output

Write:

  • 0x0:No effect.
  • 0x1:Set the output enable bit

GPIOx_OUT_CLR

  • Name: GPIO output clear register
  • Description: This register is used to disable output.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x0014
  • Reset Value: 0x00000000
表 54 GPIO output clear register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 CLR RW 0x0

Output enable clear [15:0]

Read:

  • 0x0: As input
  • 0x1:As output

Write:

  • 0x0:No effect
  • 0x1:Clear the output enable bit

GPIOx_INT_EN

  • Name: GPIO interrupt enable register
  • Description: This register is used to enable GPIO interrupt.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x0020
  • Reset Value: 0x00000000
表 55 GPIO interrupt enable register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 EN RW 0x0

Interrupt enable set [15:0]

Read:

  • 0x0: Interrupt disabled
  • 0x1: Interrupt enabled

Write:

  • 0x0: No effect
  • 0x1: Set the interrupt enable bit

GPIOx_INT_CLR

  • Name: GPIO interrupt clear register
  • Description: This register is used to disable GPIO interrupt.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x0024
  • Reset Value: 0x00000000
表 56 GPIO interrupt clear register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 CLR RW 0x0

Interrupt enable clear [15:0]

Read:

  • 0x0: Interrupt disabled
  • 0x1: Interrupt enabled

Write:

  • 0x0: No effect
  • 0x1: Clear the interrupt enable bit

GPIOx_INT_TYPE_EN

  • Name: GPIO interrupt type enable register
  • Description: This register is used to set GPIO interrupt type. If interrupt type is 0 and interrupt polarity is 0, Low-level trigger interrupt. If interrupt type is 0 and interrupt polarity is 1, High-level trigger interrupt. If interrupt type is 1 and interrupt polarity is 0, Falling edge trigger interrupt. If interrupt type is 1 and interrupt polarity is 1, Rising edge trigger interrupt.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x0028
  • Reset Value: 0x00000000
表 57 GPIO interrupt type enable register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 EN RW 0x0

Interrupt type set [15:0]

Read:

  • 0x0: LOW or HIGH level
  • 0x1: Falling edge or rising edge

Write:

  • 0x0: No effect
  • 0x1: Set the interrupt type bit

GPIOx_INT_TYPE_CLR

  • Name: GPIO interrupt type clear register
  • Description: This register is used to disable GPIO interrupt type.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x002C
  • Reset Value: 0x00000000
表 58 GPIO interrupt type clear register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 CLR RW 0h 0

Interrupt type clear [15:0]

Read:

  • 0x0: LOW or HIGH level
  • 0x1: Falling edge or rising edge

Write:

  • 0x0: No effect
  • 0x1: Clear the interrupt type bit

GPIOx_INT_POL_EN

  • Name: GPIO interrupt polarity enable register
  • Description: This register is used to enable GPIO interrupt polarity.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x0030
  • Reset Value: 0x00000000
表 59 GPIO interrupt polarity enable register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 EN RW 0h 0

Polarity-level, edge IRQ configuration [15:0]

Read:

  • 0x0: LOW level or falling edge
  • 0x1: HIGH level or rising edge

Write:

  • 0x0: No effect
  • 0x1: Set the interrupt polarity bit

GPIOx_INT_POL_CLR

  • Name: GPIO interrupt polarity disable register
  • Description: This register is used to disable GPIO interrupt polarity.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x0034
  • Reset Value: 0x00000000
表 60 GPIO interrupt polarity disable register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 CLR RW 0x0

Polarity-level, edge IRQ configuration [15:0]

Read:

  • 0x0: LOW level or falling edge
  • 0x1:HIGH level or rising edge

Write:

  • 0x0: No effect
  • 0x1: Clear the interrupt polarity bit

GPIOx_INT_STAT

  • Name: GPIO IRQ status register
  • Description: This register contains GPIO interrupt status, and used to clear the interrupt request.
  • Base Address: 0xA0010000 + x*0x1000
  • Offset: 0x0038
  • Reset Value: 0x00000000
表 61 GPIO IRQ status register
Bits Field Name RW Reset Description
31:16 RSVD R Reserved bits
15:0 STAT_CLR RW 0x0

Write one to clear interrupt request

Read:

[15:0] IRQ status Register

Write:

  • 0x0: No effect
  • 0x1: To clear the interrupt request.

MSIO_VAL

  • Name: MSIO digital input value register
  • Description: This register contains MSIO digital input value.
  • Base Address: 0xA000E000
  • Offset: 0x220
  • Reset Value:0x00000000
表 62 MSIO_VAL
Bits Field Name RW Reset Description
31:5 RSVD R Reserved bits
4:0 MSIO_VAL RO N/A MSIO digital value (when MSIO_PAD_CFG1.MSIO_A_EN = 1)

MSIO_PAD_CFG0

  • Name: MSIO pad control register 0
  • Description: This register controls MSIO pad.
  • Base Address: 0xA000C500
  • Offset: 0x3C
  • Reset Value: 0x00000000
表 63 MSIO_PAD_CFG0
Bits Field Name RW Reset Description
31:29 RSVD R Reserved bits
28:24 MSIO_OUT_EN RW 0x0

MSIO output enable (active low)

Value:
  • 0x0: Enable MSIOx output
  • 0x1: Disable MSIOx output
23:21 RSVD R Reserved bits
20:16 MSIO_IN_EN RW 0x0

MSIO input enable (active low)

Value:
  • 0x0: Enable MSIOx input
  • 0x1: Disable MSIOx input
15:13 RSVD R Reserved bits
12:8 MSIO_OUT RW 0x0

MSIO Drive level value (valid in output mode)

Value:
  • 0x0: Drive MSIOx low
  • 0x1: Drive MSIOx high
7:5 RSVD R Reserved bits
4:0 MSIO_R_EN RW 0x0

MSIO resistor enable (active low)

Value:
  • 0x0: Enable MSIOx resistor
  • 0x1: Disable MSIOx resistor

MSIO_PAD_CFG1

  • Name: MSIO pad control register 1
  • Description: This register controls MSIO pad.
  • Base Address: 0xA000C500
  • Offset: 0x40
  • Reset Value: 0x00000000
表 64 MSIO_PAD_CFG1
Bits Field Name RW Reset Description
31 *SADC_CLK_EN RW 0x0 ADC clock enable

Value:

  • 0x0: Disable ADC clock
  • 0x1: Enable ADC clock
30:28 *SADC_CLK_SEL RW 0x0 ADC clock select

Value:

  • 0x0: 16 M
  • 0x1: 8 M
  • 0x2: 4 M
  • 0x3: 2 M
  • 0x4, 0x6: 1.6 M
  • 0x5, 0x7: 1 M
27 *RSVD R Reserved bits
26:22 *MSIO_MCU_OVE RW 0x0 Use the setting from MCU domain, only valid when MCU domain is ON.
Value:
  • 0x0: Disable MSIOx digital setting
  • 0x1: Enable MSIOx digital setting
21:16 *DEP_CTRL_WR RW 0x0 Comm timer register

Deep sleep control comm timer register write bit
15 *DEP_CTRL_RD RO 0x0 Comm timer register

Deep sleep control comm timer register read bit
14:13 RSVD R Reserved bits
12:8 MSIO_R_TYPE RW 0x0

MSIO resistor type

Value:
  • 0x0: Pull down
  • 0x1: Pull up
7:5 RSVD R Reserved bits
4:0 MSIO_A_EN RW 0x0

Analog enable control for MSIO Pad

Value:
  • 0x0: Analog mode
  • 0x1: Digital mode
Note:

MSIO_PAD_CFG1 does not support fields marked with an asterisk (*).

AON_PAD_CTRL0

  • Name: AON GPIO pad control register 0
  • Description: This register controls AON GPIO pad.
  • Base Address: 0xA000C500
  • Offset: 0x50
  • Reset value: 0x00000000
表 65 AON_PAD_CTRL_0
Bits Field Name RW Reset Description
31:30 *RSVD R Reserved bits
29:28 *TIMER_CLK_SEL RW 0x0 Comm timer clock select

Value:

  • 0x0: rng_osc_clk
  • 0x1: rtc_osc_clk
  • 0x2, 0x3: rng_2_osc_clk (an RNG clock with better ppm)
27:24 *RSVD R Reserved bits
23:16 *AON_MCU_OVE RW 0x0 Use the setting from MCU domain, only valid when MCU domain is ON

Value:

  • 0x0: Disable AONx digital setting
  • 0x1: Enable AONx digital setting
15:8 AON_R_TYPE RW 0x0 Always on PAD resistor type

Value:

  • 0x0: Pull down
  • 0x1: Pull up
7:0 AON_R_EN RW 0x0

Always on PAD resister enable

Value:
  • 0x0: Enable AONx resistor
  • 0x1: Disable AONx resistor
Note:

AON_PAD_CTRL0 does not support fields marked with an asterisk (*).

AON_PAD_CTRL1

  • Name: AON GPIO pad control register 1
  • Description: This register controls AON GPIO pad.
  • Base Address: 0xA000C500
  • Offset: 0x5C
  • Reset value: 0x000000FF
表 66 AON_PAD_CTRL_1
Bits Field Name RW Reset Description
31:30 *TIMER_RD_SEL RW 0x0 Select which timer value to read

Value:

  • 0x0: calendar timer
  • 0x1: always on watchdog timer
  • 0x2: sleep timer
  • 0x3: Calendar timer alarm value
29:26 *RSVD R Reserved bits
25 *OVR_EN RW 0x0 Enable override for all stdby_n and vdd_iso_n values
24:16 *RSVD R Reserved bits
15:8 AON_OUT_VAL RW 0x0
AON PAD output value (valid when oe_n = 0):
  • 0x0: Drive AONx low
  • 0x1: Drive AONx high
7:0 AON_OUT_EN RW 0xFF

Always on PAD output enable (active low)

Value:

  • 0x0: Enable AONx output
  • 0x1: Disable AONx output
Note:

AON_PAD_CTRL1 does not support fields marked with an asterisk (*).

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