Registers

31:25

RSVD

R

Reserved bits

24

S_ST_EN

RW

0x1

Slave Select Toggle Enable.

When operating in QSPI mode with clock phase (SERIAL_CLK_PHASE) set to 0, this register controls the behavior of the slave select line (CS) between data frames. If this register field is set to 1, the CS line will toggle between consecutive data frames, with the serial clock (SCLK) being held to its default value while CS is high; if this register field is set to 0 the CS will stay low and SCLK will run continuously for the duration of the transfer.

23

RSVD

R

Reserved bits

22:21

SPI_FRAME_FORMAT

RW

0x0

SPI Frame Format:

Selects data frame format for Transmitting/Receiving the data bits.

Value:

• 0x0 (STD_SPI_FRAME_FORMAT): Standard SPI Frame Format
• 0x1 (DUAL_SPI_FRAME_FORMAT): Dual SPI Frame Format
• 0x2 (QUAD_SPI_FRAME_FORMAT): Quad SPI Frame Format
• 0x3: Reserved

20:16

DATA_FRAME_SIZE

RW

0x7

Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. When the data frame size is programmed to be less than 32 bits, the receive data is automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You are responsible for making sure that transmit data is right-justified before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data.

Note:

When SPI_FRAME_FORMAT is not set to 0x0,

• DFS value should be multiple of 2 if SPI_FRAME_FORMAT = 0x01,
• DFS value should be multiple of 4 if SPI_FRAME_FORMAT = 0x10.

Value:

• 0x3 (FRAME_04BITS): 4-bit serial data transfer
• 0x4 (FRAME_05BITS): 5-bit serial data transfer
• 0x5 (FRAME_06BITS): 6-bit serial data transfer
• 0x6 (FRAME_07BITS): 7-bit serial data transfer
• 0x7 (FRAME_08BITS): 8-bit serial data transfer
• 0x8 (FRAME_09BITS): 9-bit serial data transfer
• 0x9 (FRAME_10BITS): 10-bit serial data transfer
• 0xa (FRAME_11BITS): 11-bit serial data transfer
• 0xb (FRAME_12BITS): 12-bit serial data transfer
• 0xc (FRAME_13BITS): 13-bit serial data transfer
• 0xd (FRAME_14BITS): 14-bit serial data transfer
• 0xe (FRAME_15BITS): 15-bit serial data transfer
• 0xf (FRAME_16BITS): 16-bit serial data transfer
• 0x10 (FRAME_17BITS): 17-bit serial data transfer
• 0x11 (FRAME_18BITS): 18-bit serial data transfer
• 0x12 (FRAME_19BITS): 19-bit serial data transfer
• 0x13 (FRAME_20BITS): 20-bit serial data transfer
• 0x14 (FRAME_21BITS): 21-bit serial data transfer
• 0x15 (FRAME_22BITS): 22-bit serial data transfer
• 0x16 (FRAME_23BITS): 23-bit serial data transfer
• 0x17 (FRAME_24BITS): 24-bit serial data transfer
• 0x18 (FRAME_25BITS): 25-bit serial data transfer
• 0x19 (FRAME_26BITS): 26-bit serial data transfer
• 0x1a (FRAME_27BITS): 27-bit serial data transfer
• 0x1b (FRAME_28BITS): 28-bit serial data transfer
• 0x1c (FRAME_29BITS): 29-bit serial data transfer
• 0x1d (FRAME_30BITS): 30-bit serial data transfer
• 0x1e (FRAME_31BITS): 31-bit serial data transfer
• 0x1f (FRAME_32BITS): 32-bit serial data transfer

15:12

CTRL_FRAME_SIZE

RW

0x0

Control Frame Size. Selects the length of the control word for the Microwire frame format.

Value:

• 0x0 (SIZE_01_BIT): 1-bit Control Word
• 0x1 (SIZE_02_BIT): 2-bit Control Word
• 0x2 (SIZE_03_BIT): 3-bit Control Word
• 0x3 (SIZE_04_BIT): 4-bit Control Word
• 0x4 (SIZE_05_BIT): 5-bit Control Word
• 0x5 (SIZE_06_BIT): 6-bit Control Word
• 0x6 (SIZE_07_BIT): 7-bit Control Word
• 0x7 (SIZE_08_BIT): 8-bit Control Word
• 0x8 (SIZE_09_BIT): 9-bit Control Word
• 0x9 (SIZE_10_BIT): 10-bit Control Word
• 0xa (SIZE_11_BIT): 11-bit Control Word
• 0xb (SIZE_12_BIT): 12-bit Control Word
• 0xc (SIZE_13_BIT): 13-bit Control Word
• 0xd (SIZE_14_BIT): 14-bit Control Word
• 0xe (SIZE_15_BIT): 15-bit Control Word
• 0xf (SIZE_16_BIT): 16-bit Control Word

11

SHIFT_REG_LOOP

RW

0x0

Shift Register Loop.

Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input.

Value:

• 0x0 (NORMAL_MODE): Normal mode operation
• 0x1 (TESTING_MODE): Test mode: TX & RX shift register connected

10

RSVD

R

Reserved bits

9:8

XFE_MODE

RW

0x0

Transfer Mode.

This transfer mode is only valid when the SPI is configured as master device.

• 0x0 - Transmit & Receive
• 0x1 - Transmit Only
• 0x2 - Receive Only
• 0x3 - EEPROM Read

When SPI_FRAME_FORMAT is not set to 2'b00. There are only two valid combinations:

• 0x1 - Write
• 0x2 - Read

Value:

• 0x0 (TX_AND_RX): Transmit & receive
• 0x1 (TX_ONLY): Transmit only mode or Write (SPI_FRAME_FORMAT != 0x0)
• 0x2 (RX_ONLY): Receive only mode or Read (SPI_FRAME_FORMAT != 0x0)
• 0x3 (EEPROM_READ): EEPROM Read mode

7

SERIAL_CLK_POL

RW

0x0

Serial Clock Polarity.

Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI master is not actively transferring data on the serial bus.

Value:

• 0x0 (SCLK_LOW): Inactive state of serial clock is low
• 0x1 (SCLK_HIGH): Inactive state of serial clock is high

6

SERIAL_CLK_PHASE

RW

0x0

Serial Clock Phase.

Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal.

When SCPH = 0, data is captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data is captured on the second edge of the serial clock.

Value:

• 0x0 (SERIAL_CLK_PHASE_MIDDLE): Serial clock toggles in middle of first data bit
• 0x1 (SERIAL_CLK_PHASE_START): Serial clock toggles at start of first data bit

5:4

FRAME_FORMAT

RW

0x0

Frame Format. Selects which serial protocol transfers the data.

Value:

• 0x0 (MOTOROLA_SPI): Motorola SPI Frame Format
• 0x1 (TEXAS_SSP): Texas Instruments SSP Frame Format
• 0x2 (NS_MICROWIRE): National Microwire Frame Format
• 0x3 (RESERVED): Reserved value

3:0

RSVD

R

Reserved bits

31:16

RSVD

R

Reserved bits

15:0

NUM_DATA_FRAME

RW

0x0

Number of Data Frames.

When XFE_MODE = 0x2 or XFE_MODE = 0x3, this register field sets the number of data frames to be continuously received by the SPI. The SPI continues to receive serial data until the number of data frames received is equal to this register value plus 1, which enables you to receive up to 64 KB of data in a continuous transfer.

Note:

When the SPI is configured as a slave, this register serves no purpose.

31:1

RSVD

R

Reserved bits

0

SSI_EN

RW

0x0

SSI Enable.

Enables and disables all QSPI operations. When disabled, all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled.

Value:

• 0x0 (DISABLED): Disables Serial Transfer
• 0x1 (ENABLED): Enables Serial Transfer

31:3

RSVD

R

Reserved bits

2

MW_HSG

RW

0x0

Microwire Handshaking.

Used to enable and disable the busy/ready handshaking interface for the Microwire protocol. When enabled, the SPI checks for a ready status from the target slave, after the transfer of the last data/control bit, before clearing the SSI_BUSY status in the STAT register.

Value:

• 0x0 (DISABLE): Handshaking interface is disabled
• 0x1 (ENABLED): Handshaking interface is enabled

Note:

When the SPI is configured as a slave, this register serves no purpose.

1

MW_DIR_DW

RW

0x0

Microwire Control.

Defines the direction of the data word when the Microwire serial protocol is used.

Value:

• 0x0 (RECEIVE): SPI receives data
• 0x1 (TRANSMIT): SPI transmits data

0

MW_XFE_MODE

RW

0x0

Microwire Transfer Mode.

Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used, only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used, there must be a control word for each data word that is transmitted or received.

Value:

• 0x0 (NON_SEQUENTIAL): Non-Sequential Microwire Transfer
• 0x1 (SEQUENTIAL): Sequential Microwire Transfer

31:2

RSVD

R

Reserved bits

1:0

S_EN

RW

0x0

Slave Select Enable.

Each bit in this register corresponds to a slave select line (CSn) from the SPI master.

Value:

• 0x0 (NOT_SELECTED): No slave selected
• 0x1 (SELECTED): Slave is selected

Note:

When the SPI is configured as a slave, this register serves no purpose.

31:16

RSVD

R

Reserved bits

15:0

SSI_CLK_DIV

RW

0x0

SSI Clock Divider.

The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register. If the value is 0, the serial output clock (sclk_out) is disabled. The frequency of the sclk_out is derived from the following equation:

Note:

When the SPI is configured as a slave, this register serves no purpose.

31:3

RSVD

R

Reserved bits

2:0

TX_FIFO_THD

RW

0x0

Transmit FIFO Threshold.

Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2 – 256; this register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than or equal to the depth of the FIFO, this field is not written and retains its current value. When the number of transmit FIFO entries is less than or equal to this value, the transmit FIFO empty interrupt is triggered.

31:3

RSVD

R

Reserved bits

2:0

RX_FIFO_THD

RW

0x0

Receive FIFO Threshold.

Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2 – 256. This register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than the depth of the FIFO, this field is not written and retains its current value. When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered.

31:4

RSVD

R

Reserved bits

3:0

TX_FIFO_LEVEL

R

0x0

Transmit FIFO Level.

Contains the number of valid data entries in the transmit FIFO.

31:4

RSVD

R

Reserved bits

3:0

RX_FIFO_LEVEL

R

0x0

Receive FIFO Level.

Contains the number of valid data entries in the receive FIFO.

31:7

RSVD

R

Reserved bits

6

DATA_COLN_ERR

R

0x0

Data Collision Error.

This bit will be set if MISO input is asserted by other master, when the SPI master is in the middle of the transfer. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read.

5

TX_ERR

R

0x0

Transmission Error.

Set if the transmit FIFO is empty when a transfer is started. Data from the previous transmission is resent on the txd line. This bit is cleared when read.

Value:

• 0x0 (NO_ERROR): No Error
• 0x1 (TX_ERROR): Transmission Error

Note:

When the SPI is configured as a master, this register serves no purpose.

4

RX_FIFO_FULL

R

0x0

Receive FIFO Full.

When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared.

Value:

• 0x0 (NOT_FULL): Receive FIFO is not full
• 0x1 (FULL): Receive FIFO is full

3

RX_FIFO_NE

R

0x0

Receive FIFO Not Empty.

Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO.

Value:

• 0x0 (EMPTY): Receive FIFO is empty
• 0x1 (NOT_EMPTY): Receive FIFO is not empty

2

TX_FIFO_EMPTY

R

0x1

Transmit FIFO Empty.

When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt.

Value:

• 0x0 (NOT_EMPTY): Transmit FIFO is not empty
• 0x1 (EMPTY): Transmit FIFO is empty

1

TX_FIFO_NF

R

0x1

Transmit FIFO Not Full.

Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full.

Value:

• 0x0 (FULL): Transmit FIFO is full
• 0x1 (NOT_FULL): Transmit FIFO is not Full

0

SSI_BUSY

R

0x0

SSI Busy Flag.

When set, indicates that a serial transfer is in progress; when cleared indicates that the SPI is idle or disabled.

Value:

• 0x0 (INACTIVE): SPI is idle or disabled
• 0x1 (ACTIVE): SPI is actively transferring data

31:6

RSVD

R

Reserved bits

5

MULTI_M_CIM

RW

0x1

Multi-Master Contention Interrupt Mask.

Value:

• 0x0 (MASKED): Disable mst_intr interrupt
• 0x1 (UNMASKED): Enable mst_intr interrupt

4

RX_FIFO_FIS

RW

0x1

Receive FIFO Full Interrupt Mask

Value:

• 0x0 (MASKED): Disable rxf_intr interrupt
• 0x1 (UNMASKED): Enable rxf_intr interrupt

3

RX_FIFO_OIS

RW

0x1

Receive FIFO Overflow Interrupt Mask

Value:

• 0x0 (MASKED): Disable rxo_intr interrupt
• 0x1 (UNMASKED): Enable rxo_intr interrupt

2

RX_FIFO_UIS

RW

0x1

Receive FIFO Underflow Interrupt Mask

Value:

• 0x0 (MASKED): Disable rxu_intr interrupt
• 0x1 (UNMASKED): Enable rxu_intr interrupt

1

TX_FIFO_OIS

RW

0x1

Transmit FIFO Overflow Interrupt Mask

Value:

• 0x0 (MASKED): Disable txo_intr interrupt
• 0x1 (UNMASKED): Enable txo_intr interrupt

0

TX_FIFO_EIS

RW

0x1

Transmit FIFO Empty Interrupt Mask

Value:

• 0x0 (MASsKED): Disable txe_intr interrupt
• 0x1 (UNMASKED): Enable txe_intr interrupt

31:6

RSVD

R

Reserved bits

5

MULTI_M_CIS

R

0x0

Multi-Master Contention Interrupt Status

Value:

• 0x0 (INACTIVE): mst_intr interrupt is not active after being enabled
• 0x1 (ACTIVE): mst_intr interrupt is full after being enabled

4

RX_FIFO_FIS

R

0x0

Receive FIFO Full Interrupt Status

Value:

• 0x0 (INACTIVE): rxf_intr interrupt is not active after being enabled
• 0x1 (ACTIVE): rxf_intr interrupt is full after being enabled

3

RX_FIFO_OIS

R

0x0

Receive FIFO Overflow Interrupt Status

Value:

• 0x0 (INACTIVE): rxo_intr interrupt is not active after being enabled
• 0x1 (ACTIVE): rxo_intr interrupt is active after being enabled

2

RX_FIFO_UIS

R

0x0

Receive FIFO Underflow Interrupt Status

Value:

• 0x0 (INACTIVE): rxu_intr interrupt is not active after being enabled
• 0x1 (ACTIVE): rxu_intr interrupt is active after being enabled

1

TX_FIFO_OIS

R

0x0

Transmit FIFO Overflow Interrupt Status

Value:

• 0x0 (INACTIVE): txo_intr interrupt is not active after being enabled
• 0x1 (ACTIVE): txo_intr interrupt is active after being enabled

0

TX_FIFO_EIS

R

0x0

Transmit FIFO Empty Interrupt Status

Value:

• 0x0 (INACTIVE): txe_intr interrupt is not active after being enabled
• 0x1 (ACTIVE): txe_intr interrupt is active after being enabled

31:6

RSVD

R

Reserved bits

5

MULTI_M_CRIS

R

0x0

Multi-Master Contention Raw Interrupt Status

Value:

• 0x0 (INACTIVE): mst_intr interrupt is not active prior to be enabled
• 0x1 (ACTIVE): mst_intr interrupt is full prior to be enabled

4

RX_FIFO_FRIS

R

0x0

Receive FIFO Full Raw Interrupt Status

Value:

• 0x0 (INACTIVE): rxf_intr interrupt is not active prior to be enabled
• 0x1 (ACTIVE): rxf_intr interrupt is active prior to be enabled

3

RX_FIFO_ORIS

R

0x0

Receive FIFO Overflow Raw Interrupt Status

Value:

• 0x0 (INACTIVE): rxo_intr interrupt is not active prior to be enabled
• 0x1 (ACTIVE): rxo_intr interrupt is active prior be enabled

2

RX_FIFO_URIS

R

0x0

Receive FIFO Underflow Raw Interrupt Status

Value:

• 0x0 (INACTIVE): rxu_intr interrupt is not active prior to be enabled
• 0x1 (ACTIVE): rxu_intr interrupt is active prior to be enabled

1

TX_FIFO_ORIS

R

0x0

Transmit FIFO Overflow Raw Interrupt Status

Value:

• 0x0 (INACTIVE): txo_intr interrupt is not active prior to be enabled
• 0x1 (ACTIVE): txo_intr interrupt is active prior be enabled

0

TX_FIFO_ERIS

R

0x0

Transmit FIFO Empty Raw Interrupt Status

Value:

• 0x0 (INACTIVE): txe_intr interrupt is not active prior to be enabled
• 0x1 (ACTIVE): txe_intr interrupt is active prior be enabled

31:1

RSVD

R

Reserved bits

0

TX_FIFO_OIC

R

0x0

Clear Transmit FIFO Overflow Interrupt.

This register reflects the status of the interrupt. A read from this register clears the txo_intr interrupt; writing has no effect.

31:1

RSVD

R

Reserved bits

0

RX_FIFO_OIC

R

0x0

Clear Receive FIFO Overflow Interrupt.

This register reflects the status of the interrupt. A read from this register clears the rxo_intr interrupt; writing has no effect.

31:1

RSVD

R

Reserved bits

0

RX_FIFO_UIC

R

0x0

Clear Receive FIFO Underflow Interrupt.

This register reflects the status of the interrupt. A read from this register clears the rxu_intr interrupt; writing has no effect.

31:1

RSVD

R

Reserved bits

0

MULTI_M_IC

R

0x0

Clear Multi-Master Contention Interrupt.

This register reflects the status of the interrupt. A read from this register clears the mst_intr interrupt; writing has no effect.

31:1

RSVD

R

Reserved bits

0

INT_CLR

R

0x0

Clear Interrupts.

This register is set if any of the interrupts below are active. A read clears the txo_intr, rxu_intr, rxo_intr, and the mst_intr interrupts. Writing to this register has no effect.

31:2

RSVD

R

Reserved bits

1

TX_DMA_EN

RW

0x0

Transmit DMA Enable.

This bit enables/disables the transmit FIFO DMA channel.

Value:

• 0x0 (DISABLED): Transmit DMA disabled
• 0x1 (ENABLED): Transmit DMA enabled

0

RX_DMA_EN

RW

0x0

Receive DMA Enable.

This bit enables/disables the receive FIFO DMA channel

Value:

• 0x0 (DISABLED): Receive DMA disabled
• 0x1 (ENABLED): Receive DMA enabled

31:3

RSVD

R

Reserved bits

2:0

DMA_TX_DL

RW

0x0

Transmit Data Level.

This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TX_DMA_EN = 1.

31:3

RSVD

R

Reserved bits

2:0

DMA_RX_DL

RW

0x0

Receive Data Level.

This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMA_RX_DL +1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or above this field value + 1, and RX_DMA_EN =1.

31:0

DATA

RW

0x0

Data Register. When writing to this register, you must right-justify the data. Read data is automatically right-justified.

31:8

RSVD

R

Reserved bits

7:0

RX_SMP_DLY

RW

0x0

RX Sample Delay.

This register is used to delay the sample of the rxd input port. Each value represents a single ssi_clk delay on the sample of rxd. The maximum value is 7.

Note:

When the SPI is configured as a slave, this register serves no purpose.

31:16

RSVD

R

Reserved bits

15:11

WAIT_CYCLES

RW

0x0

Wait cycles

Number of wait cycles in Dual/Quad mode between control frames transmit and data reception. This value is specified as number of SPI clock cycles.

10

RSVD

R

Reserved bits

9:8

INST_LEN

RW

0x2

Instruction Length

Dual/Quad mode instruction length in bits.

Value:

• 0x0 (INST_LEN_0): 0-bit (No Instruction)
• 0x1 (INST_LEN_1): 4-bit Instruction
• 0x2 (INST_LEN_2): 8-bit Instruction
• 0x3 (INST_LEN_3): 16-bit Instruction

7:6

RSVD

R

Reserved bits

5:2

ADDR_LEN

RW

0x0

Address Length.

This bit defines Length of Address to be transmitted. Only after this much bits are programmed in to the FIFO the transfer can begin.

Value:

• 0x0 (ADDR_LEN_0): 0-bit Address Width
• 0x1 (ADDR_LEN_1): 4-bit Address Width
• 0x2 (ADDR_LEN_2): 8-bit Address Width
• 0x3 (ADDR_LEN_3): 12-bit Address Width
• 0x4 (ADDR_LEN_4): 16-bit Address Width
• 0x5 (ADDR_LEN_5): 20-bit Address Width
• 0x6 (ADDR_LEN_6): 24-bit Address Width
• 0x7 (ADDR_LEN_7): 28-bit Address Width
• 0x8 (ADDR_LEN_8): 32-bit Address Width
• 0x9 (ADDR_LEN_9): 36-bit Address Width
• 0xa (ADDR_LEN_10): 40-bit Address Width
• 0xb (ADDR_LEN_11): 44-bit Address Width
• 0xc (ADDR_LEN_12): 48-bit Address Width
• 0xd (ADDR_LEN_13): 52-bit Address Width
• 0xe (ADDR_LEN_14): 56-bit Address Width
• 0xf (ADDR_LEN_15): 60-bit Address Width

1:0

XFE_FORMAT_AI

RW

0x0

Address and instruction transfer format.

Selects whether QSPI will transmit instruction/address either in Standard SPI mode or the SPI mode selected in CTRL0. SPI_FRAME_FORMAT field.

Value:

• 0x0 - Instruction and Address will be sent in Standard SPI Mode.
• 0x1 - Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by CTRL0. SPI_FRAME_FORMAT.
• 0x2 - Both Instruction and Address will be sent in the mode specified by SPI_FRAME_FORMAT.
• 0x3 - Reserved.