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GR551x Datasheet

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Rev.2.6

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文档中心 > GR551x Datasheet/ Peripherals / System Watchdog/ Registers Copy URL

Registers

LOAD

Name: System Watchdog Load Register
Description: The LOAD register contains the value from which the counter is to decrease. When this register is written to, the count is immediately restarted from the new value. The minimum valid value for LOAD register is 1.
Base Address: 0xA0008000
Offset: 0x0000
Reset Value: 0xFFFFFFFF

表 78 System Watchdog Load Register
Bits	Field Name	RW	Reset	Description
31:0	COUNT	RW	0xFFFFFFFF	Reload value. A write to this register sets the current value.

VAL

Name: System Watchdog Value Register
Description: This is a read-only register used to indicate the current value of the decrementing counter.
Base Address: 0xA0008000
Offset: 0x04
Reset Value: 0xFFFFFFFF

表 79 System Watchdog Value Register
Bits	Field Name	RW	Reset	Description
31:0	COUNT	RO	0xFFFFFFFF	Current value of the watchdog counter

CTRL

Name: System Watchdog Control Register
Description: The CTRL register enables the software to control the watchdog unit.
Base Address: 0xA0008000
Offset: 0x0008
Reset Value: 0x00

表 80 System Watchdog Control Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R		Reserved bits
1	RST_EN	RW	0x0	Enable watchdog reset output. Value: 0x0: Disable the reset. 0x1: Enable the reset.
0	INT_EN	RW	0x0	Enable the interrupt event. Reload the counter from the value in LOAD register when the interrupt is enabled, after previously being disabled. Value: 0x0: Disable the counter and the interrupt. 0x1: Enable the counter and the interrupt.

INT_CLR

Name: System Watchdog Clear Interrupt Register
Description: A write of any value to the INT_CLR register clears the watchdog interrupt, and reloads the counter from the value in LOAD register.
Base Address: 0xA0008000
Offset: 0x0C
Reset Value:0x00000000

表 81 System Watchdog Clear Interrupt Register
Bits	Field Name	RW	Reset	Description
31:0	CLR	WO	0x0	Clear the watchdog interrupt event.

INT_RAW_STAT

Name: System Watchdog Raw Interrupt Status Register
Description: The INT_RAW_STAT register indicates the raw interrupt status from the counter.
Base Address: 0xA0008000
Offset: 0x10
Reset Value:0x00000000

表 82 System Watchdog Raw Interrupt Status Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	RAW_STAT	RO	0x0	Raw interrupt status from the counter

INT_STAT

Name: System Watchdog Interrupt Status Register
Description: The INT_STAT register indicates the masked interrupt status from the counter.
Base Address: 0xA0008000
Offset: 0x14
Reset Value: 0x00000000

表 83 System Watchdog Interrupt Status Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	STAT	RO	0x0	Enable interrupt status from the counter.

LOCK

Name: System Watchdog Lock Register
Description: The LOCK register disables write access to all other registers. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Write any other value disables write access.
Base Address: 0xA0008000
Offset: 0x0C00
Reset Value: 0x00000000

表 84 System Watchdog Lock Register
Bits	Field Name	RW	Reset	Description
31:1	WR_EN	RW	0x0	Enable write access to all other registers by writing 0x1ACCE551. Disable write access by writing any other value.
0	WR_EN_STAT	RW	0x0	Register write enable status Value: 0x0: Write access to all other registers is enabled. This is the default. 0x1: Write access to all other registers is disabled.

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