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GR551x Datasheet

版本：

Rev.2.6

Rev.2.7 Rev.2.6 Rev.2.5 Rev.2.4 Rev.2.3 Rev.2.2 Rev.1.9 Rev.2.8 Rev.2.9

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文档中心 > GR551x Datasheet/ Peripherals / Pin Mux / Registers Copy URL

Registers

DPAD_MUX_CTRL_00_07

Base Address: 0xA000E000
Offset: 0x240
Reset Value: 0x77777700

表 43 DPAD_MUX_CTRL_00_07
Bits	Field Name	RW	Reset	Description
31:28	DPAD_MUX_SEL_07	RW	0x7	The value of GPIO7 MUX
27:24	DPAD_MUX_SEL_06	RW	0x7	The value of GPIO6 MUX
23:20	DPAD_MUX_SEL_05	RW	0x7	The value of GPIO5 MUX
19:16	DPAD_MUX_SEL_04	RW	0x7	The value of GPIO4 MUX
15:12	DPAD_MUX_SEL_03	RW	0x7	The value of GPIO3 MUX
11:8	DPAD_MUX_SEL_02	RW	0x7	The value of GPIO2 MUX
7:4	DPAD_MUX_SEL_01	RW	0x0	The value of GPIO1 MUX
3:0	DPAD_MUX_SEL_00	RW	0x0	The value of GPIO0 MUX

DPAD_MUX_CTRL_08_15

Base Address: 0xA000E000
Offset: 0x244
Reset Value: 0x77777777

表 44 DPAD_MUX_CTRL_08_15
Bits	Field Name	RW	Reset	Description
31:28	DPAD_MUX_SEL_15	RW	0x7	Mode for DPAD 15
27:24	DPAD_MUX_SEL_14	RW	0x7	Mode for DPAD 14
23:20	DPAD_MUX_SEL_13	RW	0x7	Mode for DPAD 13
19:16	DPAD_MUX_SEL_12	RW	0x7	Mode for DPAD 12
15:12	DPAD_MUX_SEL_11	RW	0x7	Mode for DPAD 11
11:8	DPAD_MUX_SEL_10	RW	0x7	Mode for DPAD 10
7:4	DPAD_MUX_SEL_09	RW	0x7	Mode for DPAD 9
3:0	DPAD_MUX_SEL_08	RW	0x7	Mode for DPAD 8

DPAD_MUX_CTRL_16_23

Base Address: 0xA000E000
Offset: 0x248
Reset Value: 0x77777777

表 45 DPAD_MUX_CTRL_16_23
Bits	Field Name	RW	Reset	Description
31:28	DPAD_MUX_SEL_23	RW	0x7	Mode for DPAD 23
27:24	DPAD_MUX_SEL_22	RW	0x7	Mode for DPAD 22
23:20	DPAD_MUX_SEL_21	RW	0x7	Mode for DPAD 21
19:16	DPAD_MUX_SEL_20	RW	0x7	Mode for DPAD 20
15:12	DPAD_MUX_SEL_19	RW	0x7	Mode for DPAD 19
11:8	DPAD_MUX_SEL_18	RW	0x7	Mode for DPAD 18
7:4	DPAD_MUX_SEL_17	RW	0x7	Mode for DPAD 17
3:0	DPAD_MUX_SEL_16	RW	0x7	Mode for DPAD 16

DPAD_MUX_CTRL_24_31

Base Address: 0xA000E000
Offset: 0x24C
Reset Value: 0x77777777

表 46 DPAD_MUX_CTRL_24_31
Bits	Field Name	RW	Reset	Description
31:28	DPAD_MUX_SEL_31	RW	0x7	Mode for DPAD 31
27:24	DPAD_MUX_SEL_30	RW	0x7	Mode for DPAD 30
23:20	DPAD_MUX_SEL_29	RW	0x7	Mode for DPAD 29
19:16	DPAD_MUX_SEL_28	RW	0x7	Mode for DPAD 28
15:12	DPAD_MUX_SEL_27	RW	0x7	Mode for DPAD 27
11:8	DPAD_MUX_SEL_26	RW	0x7	Mode for DPAD 26
7:4	DPAD_MUX_SEL_25	RW	0x7	Mode for DPAD 25
3:0	DPAD_MUX_SEL_24	RW	0x7	Mode for DPAD 24

AON_PAD_MUX_CTRL

Base Address: 0xA000E000
Offset: 0x290
Reset value: 0x00777770

表 47 AON_PAD_MUX_CTRL
Bits	Field Name	RW	Reset	Description
31:23	RSVD	R		Reserved bits
22:20	AON_PAD_MUX_SEL_05	RW	0x7	Mode for AON PAD [5]
19	RSVD	R		Reserved bits
18:16	AON_PAD_MUX_SEL_04	RW	0x7	Mode for AON PAD [4]
15	RSVD	R		Reserved bits
14:12	AON_PAD_MUX_SEL_03	RW	0x7	Mode for AON PAD [3]
11	RSVD	R		Reserved bits
10:8	AON_PAD_MUX_SEL_02	RW	0x7	Mode for AON PAD [2]
7	RSVD	R		Reserved bits
6:4	AON_PAD_MUX_SEL_01	RW	0x7	Mode for AON PAD [1]
3:0	RSVD	R		Reserved bits

MSIO_PAD_MUX_CTRL

Base Address: 0xA000E000
Offset: 0x294
Reset Value: 0x00077777

表 48 MSIO_PAD_MUX_CTRL
Bits	Field Name	RW	Reset	Description
31:19	RSVD	R		Reserved bits
18:16	MSIO_MUX_SEL_04	RW	0x7	Mode for MSIO PAD [4]
15	RSVD	R		Reserved bits
14:12	MSIO_MUX_SEL_03	RW	0x7	Mode for MSIO PAD [3]
11	RSVD	R		Reserved bits
10:8	MSIO_MUX_SEL_02	RW	0x7	Mode for MSIO PAD [2]
7	RSVD	R		Reserved bits
6:4	MSIO_MUX_SEL_01	RW	0x7	Mode for MSIO PAD [1]
3	RSVD	R		Reserved bits
2:0	MSIO_MUX_SEL_00	RW	0x7	Mode for MSIO PAD [0]

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