Registers

Receive Buffer Register.

This register contains the data byte received on the serial input port (sin) in UART mode. The data in this register is valid only if the Data Ready (DATA_READY) bit in the Line Status Register (LINE_STAT)) is set.

Divisor Latch (Low).

This register makes up the lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART.

Note that with the Divisor Latch Registers (DIV_LATCH_LOW and DIV_LATCH_HIGH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DIV_LATCH_LOW is set, at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data.

Transmit Holding Register.

This register contains data to be transmitted on the serial output port (sout) in UART mode. Data should only be written to the TX_HDG when the TX_HDG Empty (TX_HDG_EMPTY) bit (LINE_STAT [5]) is set.

Upper 8-bit of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART.

Note that with the Divisor Latch Registers (DIV_LATCH_LOW and DIV_LATCH_HIGH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DIV_LATCH_HIGH is set, at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data.

This is used to enable/disable the generation of TX_HDG_EMPTY Interrupt.

Value:

• 0x0 (DISABLED): Disable Programmable TX_HDG_EMPTY Interrupt Mode
• 0x1 (ENABLED): Enable Programmable TX_HDG_EMPTY Interrupt Mode

Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt.

Value:

• 0x0 (DISABLED): Disable Modem Status Interrupt
• 0x1 (ENABLED): Enable Modem Status Interrupt

Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt.

Value:

• 0x0 (DISABLED): Disable Receiver Line Status Interrupt
• 0x1 (ENABLED): Enable Receiver Line Status Interrupt

Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt.

Value:

• 0x0 (DISABLED): Disable Transmit empty interrupt
• 0x1 (ENABLED): Enable Transmit empty interrupt

Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts.

Value:

• 0x0 (DISABLED): Disable Receive data Interrupt
• 0x1 (ENABLED): Enable Receive data Interrupt

RX Trigger (or RX_FIFO_TRG). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode, it is used to determine when the rts_n signal will be de-asserted only when RTC_FCT is disabled. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation.

Value:

• 0x0 (FIFO_CHAR_1): 1 character in FIFO
• 0x1 (FIFO_QUARTER_FULL): FIFO 1/4 full
• 0x2 (FIFO_HALF_FULL): FIFO 1/2 full
• 0x3 (FIFO_FULL_2): FIFO 2 less than full

TX Empty Trigger (or TX_EMPTY_TRG). This is used to select the empty threshold level at which the TX_HDG_EMPTY Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation.

Value:

• 0x0 (FIFO_EMPTY): FIFO Empty
• 0x1 (FIFO_CHAR_2): 2 characters in FIFO
• 0x2 (FIFO_QUARTER_FULL): FIFO 1/4 full
• 0x3 (FIFO_HALF_FULL): FIFO 1/2 full

DMA Mode (or DMA_MODE). This determines the DMA mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected.

Value:

• 0x0 (MODE0): Mode 0
• 0x1 (MODE1): Mode 1

TX FIFO Reset (or TX_FIFO_RST). This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals when additional DMA handshaking signals are selected.

Value:

0x1 (RESET): Transmit FIFO reset

RX FIFO Reset (or RX_FIFO_RST). This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA RX request and single signals when additional DMA handshaking signals are selected.

Value:

0x1 (RESET): Receive FIFO reset

FIFO Enable (or FIFO_EN). This enables/disables the transmit (TX) and receive (RX) FIFOs. Whenever the value of this bit is changed both the TX and RX controller portion of FIFOs is reset.

Value:

• 0x0 (DISABLED): FIFO disabled
• 0x1 (ENABLED): FIFO enabled

FIFOs Enabled (or FIFO_EN). This is used to indicate whether the FIFOs are enabled or disabled.

Value:

• 0x0 (DISABLED): FIFOs are disabled
• 0x3 (ENABLED): FIFOs are enabled

Interrupt ID (or priority index). This indicates the highest priority pending interrupt which can be one of the following types specified in Values.

Value:

• 0x0 (MODEM_STATUS): modem status
• 0x1 (NO_INTERRUPT_PENDING): no interrupt pending
• 0x2 (TX_HDG _EMPTY): TX_HDG empty
• 0x4 (RECEIVED_DATA_AVAILABLE): received data available
• 0x6 (RECEIVER_LINE_STATUS): receiver line status
• 0xC (CHARACTER_TIMEOUT): character timeout

Divisor Latch Access Bit.

This bit is used to enable reading and writing of the Divisor Latch Register (DIV_LATCH_LOW and DIV_LATCH_HIGH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers.

Value:

• 0x0 (DISABLED): Divisor Latch register is writable only when UART is not busy.
• 0x1 (ENABLED): Divisor Latch register is always readable and writable

Break Control Bit.

This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MODEM_CTRL[4], the sout line is forced low until the Break bit is cleared. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low.

Value:

• 0x0 (DISABLED): Serial output is released for data transmission
• 0x1 (ENABLED): Serial output is forced to spacing state

Stick Parity.

This bit is used to force parity value. When PARITY_EN, EVEN_PARITY_SEL and STICK_PARITY are set to 1, the parity bit is transmitted and checked as logic 0. If PARITY_EN and Stick Parity are set to 1 and EVEN_PARITY_SEL is a logic 0, then parity bit is transmitted and checked as a logic 1. If this bit is set to 0, Stick Parity is disabled.

Value:

• 0x0 (DISABLED): STICK_PARITY disabled
• 0x1 (ENABLED): STICK_PARITY enabled

Even Parity Select.

This is used to select between even and odd parity, when parity is enabled (PEN set to one). If this bit is set to one, an even number of logic '1's is transmitted or checked. If set to zero, an odd number of logic '1's is transmitted or checked.

Value:

• 0x0 (ODD_PARITY): an odd parity is transmitted or checked
• 0x1 (EVEN_PARITY): an even parity is transmitted or checked

Parity Enable.

This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively.

Value:

• 0x0 (DISABLED): disable parity
• 0x1 (ENABLED): enable parity

Number of Stop bits.

This is used to select the number of Stop bits per character that the peripheral will transmit and receive. If set to zero, one stop bit is transmitted in the serial data.

If this bit is set to one and the Data bits are set to 5 (LINE_CTRL [1:0] set to zero), one and a half Stop bits are transmitted. Otherwise, two Stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver will only check the first Stop bit.

Note:

The Stop bit duration implemented by UART may appear longer due to idle time inserted between characters for some configurations and baud clock divisor values in the transmit direction.

Value:

• 0x0 (STOP_1BIT): 1 stop bit
• 0x1 (STOP_1_5BIT_OR_2BIT): 1.5 stop bits when DATA_LEN_SEL (LINE_CTRL[1:0]) is zero, else 2 stop bit

Data Length Select (or CLS as used in legacy).

When DATA_LEN_SEL_E in LCR_EXT is set to 0, this register is used to select the number of data bits per character that the peripheral will transmit and receive.

Value:

• 0x0 (CHAR_5BITS): 5 data bits per character
• 0x1 (CHAR_6BITS): 6 data bits per character
• 0x2 (CHAR_7BITS): 7 data bits per character
• 0x3 (CHAR_8BITS): 8 data bits per character

LoopBack Bit.

This is used to put the UART into a diagnostic mode for test purposes.

Value:

• 0x0 (DISABLED): Loopback mode disabled
• 0x1 (ENABLED): Loopback mode enabled

Request to Send.

This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data.

Value:

• 0x0 (INACTIVE): Request to Send rts_n de-asserted (logic 1)
• 0x1 (ACTIVE): Request to Send rts_n asserted (logic 0)

Receiver FIFO Error bit.

This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO.

This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO.

Value:

• 0x0 (NO_RX_FIFO_ERROR): No error in RX FIFO
• 0x1 (RX_FIFO_ERROR): Error in RX FIFO

Transmitter Empty bit.

If FIFO is enabled (FIFO_CTRL[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty.

Value:

• 0x0 (DISABLED): Transmitter not empty
• 0x1 (ENABLED): Transmitter empty

Transmit Holding Register Empty bit.

If TX_HDG_EMPTY mode is disabled (INT_EN[7] set to zero) and regardless of FIFO's being implemented/ enabled or not, this bit indicates that the TX_HDG or TX FIFO is empty.

Value:

• 0x0 (DISABLED): TX_HDG_EMPTY interrupt control is disabled
• 0x1 (ENABLED): TX_HDG_EMPTY interrupt control is enabled

Break Interrupt bit.

This is used to indicate the detection of a break sequence on the serial input data.

Value:

• 0x0 (NO_BREAK): No break sequence detected
• 0x1 (BREAK): Break sequence detected

Framing Error bit.

This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP_BITS bit in the received data.

Value:

• 0x0 (NO_FRAMING_ERROR): no framing error
• 0x1 (FRAMING_ERROR): framing error

Parity Error bit.

This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PARITY_EN) bit (LINE_CTRL[3]) is set.

Value:

• 0x0 (NO_PARITY_ERROR): no parity error
• 0x1 (PARITY_ERROR): parity error

Overrun error bit.

This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read.

Value:

• 0x0 (NO_OVER_RUN_ERROR): no overrun error
• 0x1 (OVER_RUN_ERROR): overrun error

Data Ready bit.

This is used to indicate that the receiver contains at least one character in the RX_BUF or the receiver FIFO. This bit is cleared when the receiver FIFO is empty, in the FIFO mode.

Value:

• 0x0 (NOT_READY): data not ready
• 0x1 (READY): data ready

Clear to Send.

This is used to indicate the current state of the modem control line cts_n. That is, this bit is the complement cts_n. When the Clear to Send input (cts_n) is asserted, it is an indication that the modem or data set is ready to exchange data with the UART.

In Loopback Mode (MODEM_CTRL[4] set to one), CLR_SEND is the same as MODEM_CTRL[1] (REQ_TO_SEND).

Value:

• 0x0 (DEASSERTED): cts_n input is de-asserted (logic 1)
• 0x1 (ASSERTED): cts_n input is asserted (logic 0)

Delta Clear to Send.

This is used to indicate that the modem control line cts_n has changed since the last time the MODEM_STAT was read.

Reading the MODEM_STAT clears the DELTA_CLR_SEND bit. In Loopback Mode (MODEM_CTRL[4] set to one), DELTA_CLR_SEND reflects changes on MODEM_CTRL[1] (REQ_TO_SEND).

Note:

If the DELTA_CLR_SEND bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DELTA_CLR_SEND bit will get set when the reset is removed if the cts_n signal remains asserted.

Value:

• 0x0 (NO_CHANGE): no change on cts_n since last read of MODEM_STAT
• 0x1 (CHANGE): change on cts_n since last read of MODEM_STAT

31:8

RSVD

R

Reserved bits

7:0

SCRATCHPAD

RW

This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART.

31:8

RSVD

R

Reserved bits

7:0

SHADOW_RX_BUFn

R

Shadow Receive Buffer Register n. This is a shadow register for the RX_BUF and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode. The data in this register is valid only if the Data Ready (DATA_READY) bit in the Line Status Register (LINE_STAT) is set.

• If FIFOs are disabled (FIFO_CTRL[0] set to zero), the data in the RX_BUF must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error.
• If FIFOs are enabled (FIFO_CTRL[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur.

31:8

RSVD_STHRn

R

SHADOW_TX_HDG0 31 to SHADOW_TX_HDGN_REG_SIZE Reserved bits read as 0.

7:0

SHADOW_TX_HDGn

W

0x0

Shadow Transmit Holding Register n. This is a shadow register for the TX_HDG and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode. Data should only be written to the TX_HDG when the TX_HDG Empty (TX_HDG_EMPTY) bit (LINE_STAT[5]) is set.

• If FIFOs are disabled (FIFO_CTRL[0] set to zero) and TX_HDG_EMPTY is set, writing a single character to the TX_HDG clears the TX_HDG_EMPTY. Any additional writes to the TX_HDG before the TX_HDG_EMPTY is set again causes the TX_HDG data to be overwritten.
• If FIFOs are enabled (FIFO_CTRL[0] set to one) and TX_HDG_EMPTY is set, x number of characters of data may be written to the TX_HDG before the FIFO is full. The number x (default=128) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.

31:1

RSVD

R

Reserved bits

0

FIFO_ACCESS

R

0x0

This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are implemented and enabled. When FIFOs are not implemented or not enabled, it allows the RX_BUF to be written by the master and the TX_HDG to be read by the master.

Note:

When the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty.

Value:

• 0x0 (DISABLED): FIFO access mode disabled
• 0x1 (ENABLED): FIFO access mode enabled

31:5

RSVD

R

Reserved bits

4

RX_FIFO_FULL

R

0x0

Receive FIFO Full.

This is used to indicate that the receive FIFO is completely full. This bit is cleared when the RX FIFO is no longer full.

Value:

• 0x0 (NOT_FULL): Receive FIFO not full
• 0x1 (FULL): Receive FIFO full

3

RX_FIFO_EMPTY

R

0x0

Receive FIFO Not Empty.

This is used to indicate that the receive FIFO contains one or more entries. This bit is cleared when the RX FIFO is empty.

Value:

• 0x0 (EMPTY): Receive FIFO is empty
• 0x1 (NOT_EMPTY): Receive FIFO is not empty

2

TX_FIFO_EMPTY

R

0x1

Transmit FIFO Empty.

This is used to indicate that the transmit FIFO is completely empty. This bit is cleared when the TX FIFO is no longer empty.

Value:

• 0x0 (NOT_EMPTY): Transmit FIFO is not empty
• 0x1 (EMPTY): Transmit FIFO is empty

1

TX_FIFO_FULL

R

0x1

Transmit FIFO Not Full.

This is used to indicate that the transmit FIFO in not full. This bit is cleared when the TX FIFO is full.

Value:

• 0x0 (FULL): Transmit FIFO is full
• 0x1 (NOT_FULL): Transmit FIFO is not full

0

RSVD

R

Reserved bit

31:8

RSVD

R

Reserved bits

7:0

TX_FIFO_LEVEL

R

0x0

Transmit FIFO Level

This indicates the number of data entries in the transmit FIFO.

31:8

RSVD

R

Reserved bits

7:0

RX_FIFO_LEVEL

R

0x0

Receive FIFO Level

This is indicates the number of data entries in the receive FIFO.

31:3

RSVD

R

Reserved bits

2

TX_FIFO_RST

W

0x0

TX FIFO Reset.

This is a shadow register for the TX FIFO Reset bit (FIFO_CTRL[2]). This can be used to remove the burden on software having to store previously written FIFO_CTRL values (which are pretty static) just to reset the transmit FIFO.

1

RX_FIFO_RST

W

0x0

RX FIFO Reset.

This is a shadow register for the RX FIFO Reset bit (FIFO_CTRL[1]). This can be used to remove the burden on software having to store previously written FIFO_CTRL values (which are pretty static) just to reset the receive FIFO.

0

UART_RST

W

0x0

UART Reset.

This asynchronously resets the UART and synchronously removes the reset assertion. For a two-clock implementation both PCLK and SCLK domains will be reset.

Value:

• 0x0 (NO_RESET): No UART Reset
• 0x1 (RESET): UART reset

31:1

RSVD

R

Reserved bits

0

SHADOW_REQ_SEND

RW

0x0

Shadow Request to Send.

This is a shadow register for the REQ_TO_SEND bit (MODEM_CTRL [1]), this can be used to remove the burden of having to performing a read modify write on the MODEM_CTRL. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data.

Value:

• 0x0 (DEASSERTED): Shadow Request to Send uart_rts_n logic 1
• 0x1 (ASSERTED): Shadow Request to Send uart_rts_n logic 0

31:1

RSVD

R

Reserved bits

0

SHADOW_BREAK_CB

RW

0x0

Shadow Break Control Bit.

This is a shadow register for the Break bit (LINE_CTRL[6]). This can be used to remove the burden of having to performing a read modify write on the LINE_CTRL. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MODEM_CTRL [4], the sout line is forced to be low until the Break bit is cleared.

Value:

• 0x0 (NO_BREAK): No spacing on serial output
• 0x1 (BREAK): Serial output forced to the spacing

31:1

RSVD

R

Reserved bits

0

SHADOW_DMA_MODE

RW

0x0

Shadow DMA Mode.

This is a shadow register for the DMA mode bit (FIFO_CTRL[3]). This can be used to remove the burden of having to store the previously written value to the FIFO_CTRL in memory and having to mask this value so that only the DMA Mode bit gets updated.

Value:

• 0x0 (MODE_0): Mode 0
• 0x1 (MODE_1): Mode 1

31:1

RSVD

R

Reserved bits

0

SHADOW_FIFO_EN

RW

0x0

Shadow FIFO Enable.

This is a shadow register for the FIFO enable bit (FIFO_CTRL[0]). This can be used to remove the burden of having to store the previously written value to the FIFO_CTRL in memory and having to mask this value so that only the FIFO enable bit gets updated. This enables/disables the transmit (TX) and receive (RX) FIFO's. If this bit is set to zero (disabled) after being enabled then both the TX and RX controller portions of FIFO's will be reset.

Value:

• 0x0 (DISABLED): FIFOs are disabled
• 0x1 (ENABLED): FIFOs are enabled

31:2

RSVD

R

Reserved bits

1:0

SHADOW_RX_TRG

RW

0x0

Shadow RX Trigger.

This is a shadow register for the RX trigger bits (FIFO_CTRL[7:6]). This can be used to remove the burden of having to store the previously written value to the FIFO_CTRL in memory and having to mask this value so that only the RX trigger bit gets updated.

Value:

• 0x0 (FIFO_CHAR_1): 1 character in FIFO
• 0x1 (FIFO_QUARTER_FULL): FIFO 1/4 full
• 0x2 (FIFO_HALF_FULL): FIFO 1/2 full
• 0x3 (FIFO_FULL_2): FIFO 2 less than full

31:2

RSVD

R

Reserved bits

1:0

SHADOW_TX_TRG

RW

0x0

Shadow TX Empty Trigger.

This is a shadow register for the TX empty trigger bits (FIFO_CTRL[5:4]). This can be used to remove the burden of having to store the previously written value to the FIFO_CTRL in memory and having to mask this value so that only the TX empty trigger bit gets updated.

Value:

0x0 (FIFO_EMPTY): FIFO empty

0x1 (FIFO_CHAR_2): 2 characters in FIFO

0x2 (FIFO_QUARTER_FULL): FIFO 1/4 full

0x3 (FIFO_HALF_FULL): FIFO 1/2 full

31:1

RSVD

R

Reserved bits

0

HALT_TX

RW

0x0

Halt TX.

This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled.

Value:

• 0x0 (DISABLED): Halt Transmission disabled
• 0x1 (ENABLED): Halt Transmission enabled

31:1

RSVD

R

Reserved bits

0

DMA_SW_ACK

W

DMA Software Acknowledge.

This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the UART should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing' and it is not necessary to clear this bit.

Value:

0x1 (SOFT_ACK): DMA software acknowledge

31:4

RSVD

R

Reserved bits

3:0

DIV_LATCH_FRACTION

RW

0x0

Fractional part of divisor.

The fractional value is added to integer value set by DIV_LATCH_HIGH, and DIV_LATCH_LOW. Fractional value is determined by (Divisor Fraction value)/(2^DIV_LATCH_FRACTION_SIZE).