Registers

31:1

RSVD

R

Reserved bits

0

I2S_EN

RW

0x0

I2S enable.

This bit enables or disables I2S. A disable on this bit overrides any other block or channel enables and flushes all FIFOs.

Value:

• 0x0: I2S disabled.
• 0x1: I2S enabled

31:1

RSVD

R

Reserved bits

0

RX_EN

RW

0x0

Receiver block enable.

This bit enables or disables the receiver. A disable on this bit overrides any individual receive channel enables.

Value:

• 0x0: Receiver disabled
• 0x1: Receiver enabled

31:1

RSVD

R

Reserved bits

0

TX_EN

RW

0x0

Transmitter block enable.

This bit enables or disables the transmitter. A disable on this bit overrides any individual transmit channel enables.

Value:

• 0x0: Transmitter disabled
• 0x1: Transmitter enabled

31:1

RSVD

R

Reserved bits

0

CLK_EN

RW

0x0

Clock Generation enable/disable.

This bit enables or disables the clock generation signals when I2S is a master.

Value:

• 0x0: Clock generation disabled
• 0x1: Clock generation enabled

Note:

When the I2S is configured as a slave, this register serves no purpose.

31:5

RSVD

R

Reserved bits

4:3

WS_SCLK

RW

0x0

These bits are used to program the number of SCLK cycles for which the word select line (ws_out) stays in the left or right sample mode. The I2S Clock Generation block must be disabled (CLK_EN [0] = 0) prior to any changes in this value.

Value:

• 0x0: 16 SCLK cycles
• 0x1: 24 SCLK cycles
• 0x2: 32 SCLK cycles

2:0

SCLK_GAT

RW

0x0

These bits are used to program the gating of SCLK. The programmed gating value must be less than or equal to the largest configured/programmed audio resolution to prevent the truncating of RX/TX data. The I2S Clock Generation block must be disabled (CLK_EN[0] = 0) before making any changes in this value.

Values:

• 0x0 (NO_CLOCK_GATING): Clock gating is disabled
• 0x1 (CLOCK_CYCLES_12): Gating after 12 SCLK cycles
• 0x2 (CLOCK_CYCLES_16): Gating after 16 SCLK cycles
• 0x3 (CLOCK_CYCLES_20): Gating after 20 SCLK cycles
• 0x4 (CLOCK_CYCLES_24): Gating after 24 SCLK cycles

Note:

This register is only relevant when component is configured to be a master (I2S_MODE_EN = 1).

31:1

RSVD

W

Reserved bits

0

RX_FIFO_RST

W

0x0

Receiver FIFO Reset.

Writing a 1 to this register flushes all the RX FIFOs (this is a self-clear bit). The Receiver Block must be disabled before writing to this bit.

Value:

• 0x0: Do not flush the RX FIFO
• 0x1: Flush the RX FIFO

31:1

RSVD

W

Reserved bits

0

TX_FIFO_RST

W

0x0

Transmitter FIFO Reset.

Writing a 1 to this register flushes all the TX FIFOs (this is a self-clear bit). The Transmitter Block must be disabled prior to writing this bit.

Value:

• 0x0: Do not flush the TX FIFO
• 0x1: Flush the TX FIFO

31:0

LEFT_RX_BUF

R

0x0

The left stereo data received serially from the receive channel input (sdi). If the RX FIFO is full and the two-stage read operation (for instance, a read from LEFT_RX_BUF followed by a read from RIGHT_RX_BUF) is not performed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs. (Data already in the RX FIFO is preserved.)

Note:

Before reading this register again, the right stereo data must be read from RIGHT_RX_BUFx or the status/interrupts will not be valid.

31:0

LEFT_TX_HDG

W

0x0

The left stereo data to be transmitted serially through the transmit channel output (sdo) is written through this register.

Writing is a two-stage process:

• A write to this register passes the left stereo sample to the transmitter
• This MUST be followed by writing the right stereo sample to the RIGHT_TX_HDG register

Data must only be written to the FIFO when it is not full. Any attempt to write to a full FIFO results in that data being lost and an overrun interrupt being generated.

31:0

RIGHT_RX_BUF

R

0x0

The right stereo data received serially from the receive channel input (SDI) is read through this register. If the RX FIFO is full and the two-stage read operation (for instance, read from LEFT_RX_BUF followed by a read from RIGHT_RX_BUF) is not performed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs. (Data already in the RX FIFO is preserved.)

Note:

Prior to reading this register, the left stereo data must be read from LEFT_RX_BUF, or the status/interrupts will not be valid.

31:0

RIGHT_TX_HDG

W

0x0

The right stereo data to be transmitted serially through the transmit channel output (SDO) is written through this register.

Writing is a two-stage process:

• A left stereo sample must be written to the LEFT_TX_HDG register
• A write to this register passes the right stereo sample to the transmitter

Data should only be written to the FIFO when it is not full. Any attempt to write to a full FIFO results in that data being lost and an overrun interrupt being generated.

31:1

RSVD

R

Reserved bits

0

RX_CH_EN

RW

0x1

Receive channel enable. This bit enables/disables a receive channel.

On enable, the channel begins receiving on the next left stereo cycle.

A global disable of I2S (EN[0] = 0) or the Receiver block (RX_EN[0] = 0) overrides this value.

Value:

• 0x0: Receive Channel Disable
• 0x1: Receive Channel Enable

31:1

RSVD

R

Reserved bits

0

TX_CH_EN

RW

0x1

Transmit channel enable. This bit enables/disables a transmit channel.

On enable, the channel begins transmitting on the next left stereo cycle.

A global disable of I2S (EN[0] = 0) or Transmitter block (TX_EN[0] = 0) overrides this value.

Value:

• 0x0: Transmit Channel Disable
• 0x1: Transmit Channel Enable

31:3

RSVD

R

Reserved bits

2:0

WORD_LEN

RW

0x5

These bits are used to program the desired data resolution of the receiver and enables the LSB of the incoming left (or right) word to be placed in the LSB of the LEFT_RX_BUF (or RIGHT_RX_BUF) register.

Programmed data resolution must be less than or equal to 0x5. If the selected resolution is greater than the 0x5, the receive channel defaults back to 0x5.

The channel must be disabled prior to any changes in this value (RX_EN0[0] = 0).

Value:

• 0x0: Ignore the word length
• 0x1: 12-bit data resolution of the receiver.
• 0x2: 16-bit data resolution of the receiver.
• 0x3: 20-bit data resolution of the receiver.
• 0x4: 24-bit data resolution of the receiver.
• 0x5: 32-bit data resolution of the receiver.

31:3

RSVD

R

Reserved bits

2:0

WORD_LEN

RW

0x5

These bits are used to program the data resolution of the transmitter and ensures the MSB of the data is transmitted first.

Programmed resolution must be less than or equal to 0x5. If the selected resolution is greater than 0x5, the transmit channel defaults back to 0x5.

The channel must be disabled prior to any changes in this value (TX_EN [0] = 0).

Value:

• 0x0: Ignore the word length
• 0x1: 12-bit data resolution of the transmitter.
• 0x2: 16-bit data resolution of the transmitter.
• 0x3: 20-bit data resolution of the transmitter.
• 0x4: 24-bit data resolution of the transmitter.
• 0x5: 32-bit data resolution of the transmitter.

31:6

RSVD

R

Reserved bits

5

TX_FIFO_OVER

R

0x0

Status of Data Overrun interrupt for the TX channel.

This bit specifies whether the TX FIFO write is valid or an overrun. Attempt to write to full TX FIFO.

Value:

• 0x0: TX FIFO write valid
• 0x1: TX FIFO write overrun

4

TX_FIFO_EMPTY

R

0x1

Status of Transmit Empty Trigger interrupt.

This bit specifies whether the TX FIFO trigger level has reached or not. TX FIFO is empty.

Value:

• 0x0: TX FIFO trigger level is reached
• 0x1: TX FIFO trigger level is not reached

3:2

RSVD

R

Reserved bits

1

RX_FIFO_OVER

R

0x0

Status of Data Overrun interrupt for the RX channel. Incoming data lost due to a full RX FIFO.

Value:

• 0x0: RX FIFO write valid
• 0x1: RX FIFO write overrun

0

RX_DATA_AVL

R

0x0

Status of Receive Data Available interrupt. This bit denotes the status of the RX FIFO trigger level.

Value:

• 0x0: RX FIFO trigger level is not reached
• 0x1: RX FIFO trigger level is reached

31:6

RSVD

R

Reserved bits

5

TX_FOM

RW

0x1

Mask TX FIFO Overrun interrupt.

This bit masks or unmasks a TX FIFO overrun interrupt.

Value:

• 0x0: Enable TX FIFO Overrun interrupt
• 0x1: Disable TX FIFO Overrun interrupt

4

TX_FEM

RW

0x1

Mask TX FIFO Empty interrupt.

This bit masks or unmasks a TX FIFO Empty interrupt.

Value:

• 0x0: Enable TX FIFO Empty interrupt
• 0x1: Disable TX FIFO Empty interrupt

3:2

RSVD

R

Reserved bits

1

RX_FOM

RW

0x1

Mask RX FIFO Overrun interrupt.

This bit masks or unmasks an RX FIFO Overrun interrupt.

Value:

• 0x0: Enable RX FIFO Overrun interrupt
• 0x1: Disable RX FIFO Overrun interrupt

0

RX_DAM

RW

0x1

Mask RX FIFO Data Available interrupt.

This bit masks or unmasks an RX FIFO Data Available interrupt.

Value:

• 0x0: Enable RX FIFO data available interrupt
• 0x1: Disable RX FIFO data available interrupt

31:1

RSVD

R

Reserved bits

0

RX_CLR_FDO

R

0x0

Read this bit to clear the RX FIFO Data Overrun interrupt.

Value:

• 0x0: RX FIFO write valid
• 0x1: RX FIFO write overrun

31:1

RSVD

R

Reserved bits

0

TX_CLR_FDO

R

0X0

Read this bit to clear the TX FIFO Data Overrun interrupt.

Value:

• 0x0: TX FIFO write valid
• 0x1: TX FIFO write overrun

31:4

RSVD

R

Reserved bits

3:0

RX_FIFO_TL

RW

0x8

These bits program the trigger level in the RX FIFO at which the Received Data Available interrupt is generated.

Trigger Level = Programmed Value + 1

Value:

• 0x0: Interrupt trigger when FIFO level is 1.
• 0x1: Interrupt trigger when FIFO level is 2.
• 0x2: Interrupt trigger when FIFO level is 3.
• 0x3: Interrupt trigger when FIFO level is 4.
• 0x4: Interrupt trigger when FIFO level is 5.
• 0x5: Interrupt trigger when FIFO level is 6.
• 0x6: Interrupt trigger when FIFO level is 7.
• 0x7: Interrupt trigger when FIFO level is 8.
• 0x8: Interrupt trigger when FIFO level is 9.
• 0x9: Interrupt trigger when FIFO level is 10.
• 0xA: Interrupt trigger when FIFO level is 11.
• 0xB: Interrupt trigger when FIFO level is 12.
• 0xC: Interrupt trigger when FIFO level is 13.
• 0xD: Interrupt trigger when FIFO level is 14.
• 0xE: Interrupt trigger when FIFO level is 15.
• 0xF: Interrupt trigger when FIFO level is 16.

31:4

RSVD

R

Reserved bits

3:0

TX_FIFO_TL

RW

0x8

These bits program the trigger level in the TX FIFO at which the Empty Threshold Reached Interrupt is generated.

Trigger Level = TX_FIFO_TL

Value:

• 0x0: Interrupt trigger when FIFO level is 1.
• 0x1: Interrupt trigger when FIFO level is 2.
• 0x2: Interrupt trigger when FIFO level is 3.
• 0x3: Interrupt trigger when FIFO level is 4.
• 0x4: Interrupt trigger when FIFO level is 5.
• 0x5: Interrupt trigger when FIFO level is 6.
• 0x6: Interrupt trigger when FIFO level is 7.
• 0x7: Interrupt trigger when FIFO level is 8.
• 0x8: Interrupt trigger when FIFO level is 9.
• 0x9: Interrupt trigger when FIFO level is 10.
• 0xA: Interrupt trigger when FIFO level is 11.
• 0xB: Interrupt trigger when FIFO level is 12.
• 0xC: Interrupt trigger when FIFO level is 13.
• 0xD: Interrupt trigger when FIFO level is 14.
• 0xE: Interrupt trigger when FIFO level is 15.
• 0xF: Interrupt trigger when FIFO level is 16.

31:1

RSVD

W

Reserved bits

0

RX_FIFO_RST

W

0x0

Receive Channel FIFO Reset.

Writing a 1 to this register flushes an individual RX FIFO (This is a self-clear bit.). A RX channel or block must be disabled prior to writing to this bit.

Value:

• 0x0: Do not flush an individual RX FIFO.
• 0x1: Flush an individual RX FIFO.

31:1

RSVD

W

Reserved bits

0

TX_FIFO_RST

W

0x0

Transmit Channel FIFO Reset.

Writing a 1 to this register flushes an individual TX FIFO (This is a self-clear bit.). A TX channel or block must be disabled prior to writing to this bit.

Value:

• 0x0: Do not flush an individual TX FIFO.
• 0x1: Flush an individual TX FIFO.

31:1

RSVD

R

Reserved bits

0

RX_DMA

RW

0x0

Receiver Block DMA Register.

These bits are used to cycle repeatedly through the enabled receive channel, reading stereo data pairs.

31:1

RSVD

W

Reserved bits

0

RST_RX_DMA

W

0x0

Reset Receiver Block DMA Register.

Writing a 1 to this self-clearing register resets the RX_DMA register mid-cycle to point to the enabled Receive channel.

Value:

• 0x0: No effect.
• 0x1: Reset receiver block DMA register.

31:1

RSVD

R

Reserved bits

0

TX_DMA

RW

0x0

Transmitter Block DMA Register.

These bits are used to cycle repeatedly through the enabled transmit channel to allow writing of stereo data pairs.

31:1

RSVD

W

Reserved bits

0

RST_TX_DMA

W

0x0

Reset Transmitter Block DMA Register.

Writing a 1 to this self-clearing register resets the TX_DMA register mid-cycle to point to the enabled Transmit channel.

Value:

• 0x0: No effect.
• 0x1: Reset transmitter block DMA register.

31:19

RSVD

R

Reserved bits

18

CLK_SRC_SEL

RW

0x1

clock divider source select 0:96 M, 1:32 M

17

RSVD

R

Reserved bits

16

DIV_EN

RW

0x0

Enable I2S clock divider

15:12

RSVD

R

Reserved bits

11:0

DIV

RW

0x8

ratio = 1/(div + 2). Duty cycle is not 50 when the number is odd.

For example:

div = 0, ratio = 1/2