文档反馈

需包含文字性建议

感谢关注汇顶文档，期待您的宝贵建议！

感谢您的反馈，祝您愉快！

GR551x Datasheet

版本：

Rev.2.6

Rev.2.7 Rev.2.6 Rev.2.5 Rev.2.4 Rev.2.3 Rev.2.2 Rev.1.9 Rev.2.8 Rev.2.9

产品页面

开发者社区

文档反馈

文档中心 > GR551x Datasheet/ Peripherals / Execute-in-place QSPI (XQSPI)/ XIP_Cache Registers Copy URL

XIP_Cache Registers

CACHE_CTRL0

Name: XQSPI cache Control 0 Register
Description: This register performs the main control of XIP cache.
Base Address: 0xA000D000
Offset: 0x00
Reset Value: 0x00000011

表 208 Control 0 Register
Bits	Field Name	RW	Reset	Description
31:5	RSVD	R		Reserved bits
4	HIT_MISS_CLR	RW	0x1	Clear Hit/Miss Counters Value: 0x0: Hit/Miss Counters in Normal Mode 0x1: Hit/Miss Counters in Clear Mode
3	FIFO_CLR	RW	0x0	Clear LFU FIFO Value: 0x0: FIFO in Normal Mode 0x1: FIFO in Clear Mode
2	Reserved	R		Reserved bits
1	TAG_FLUSH_EN	RW	0x0	Enable Tag Memory Flush Tag memory will get flushed unless tag_ret is enabled (Tag_ret signal lives in CPU register space). Value: 0x0: Tag memory Flush is disabled. 0x1: Tag memory Flush is enabled.
0	CACHE_EN	RW	0x1	Value: 0x0: Cache enabled. 0x1: Cache disabled.

CACHE_CRTL1

Name: XQSPI cache Control 1 Register
Description: This register is used to configure Bus Write/Read.
Base Address: 0xA000D000
Offset: 0x04
Reset Value: 0x00000110

表 209 Control 1 Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R		Reserved bits
11	BUS_MUX_EN	RW	0x0	Value: 0x0: enable 0x1: disable
10:8	BUS_MUX_SRC	RW	0x1	Select 1 of 8 debug-bus configurations. Debug-bus is 8-bit bus.
7:4	BIAS_TRIM	RW	0x1	Bias TRIM signal
3:2	RW_MARGIN_CTRL	RW	0x0	Read and write margin control
1	WR_MARGIN	RW	0x0	Write margin
0	RD_MARGIN	RW	0x0	Read margin

CACHE_HIT_COUNT

Name: XQSPI cache Hits Counter Register
Description: Cache Hits counter
Base Address: 0xA000D000
Offset: 0x08
Reset Value: 0x00000000

表 210 Hits Counter Register
Bits	Field Name	RW	Reset	Description
31:0	HIT_COUNT	R	0x0	Cache hit counter

CACHE_MISS_COUNT

Name: XQSPI cache Miss Counter Register
Description: Cache Miss counter
Base Address: 0xA000D000
Offset: 0x0C
Reset Value: 0x00000000

表 211 Miss Counter Register
Bits	Field Name	RW	Reset	Description
31:0	MISS_COUNT	R	0x0	Cache miss counter

CACHE_STAT

Name: XQSPI cache Status Register
Description: This is a read-only register used to indicate the current tag flush status.
Base Address: 0xA000D000
Offset: 0x10
Reset Value: 0x00000000

表 212 Status Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	STAT	R	0x0	Tag_flush_busy status. Value: 0x0: Idle 0x1: Busy

扫描关注

打开微信，使用“扫一扫”即可关注。