Functional Description
Block Diagram
The calendar timer includes:
- One alarm
- One 32-bit up counter
- One 32-bit alarm register
- One clock divider
- One wrap-around counter
Clocks
The calendar timer is working in 32.768 kHz RTC clock with 5 divide options controlled by register CLK_SEL.
The options are in the below table:
| Value | Option |
|---|---|
| 0 | Bypass divider. RTC 32.768 kHz clock |
| 1 | /32: 1.024 kHz clock |
| 2 | /64: 512 Hz clock |
| 3 | /128: 256 Hz clock |
| 4 | /256: 128 Hz clock |
| 5 - 7 | No clock |
Counter Load
- To load value to up counter, program desired value to VAL then set write-only register VAL_LOAD = 1. It takes effect in 1 – 3 configured clock cycles as well. MCU can check read-only register VAL_RD to confirm (optional).
- To load value to alarm register, program desired value to VAL then set write-only register ALARM_VAL_LOAD = 1. It takes effect in 1 – 3 configured clock cycles as well. MCU can check read-only register VAL_RD to confirm (optional).
Timer Enable and Disable
- To enable the block, set EN = 1.
- To disable the block, set EN = 0.
Note:
Before enabling the block, make sure the value is loaded successfully.
Counter
The up counter starts to count up once the block is enabled. WRAP_CNT increments when the counter wraps around. An interrupt is generated as well.
Alarm
The calendar timer generates an alarm interrupt when the value of up counter equals to that of alarm register.
Reading Timer Value
Set TIMER_READ_SEL with its values in the table below, and read the corresponding values of the counter.
| Value | Content |
|---|---|
| 0 | Calendar timer up counter value |
| 1 | Always-on watchdog down counter value |
| 2 | Sleep timer counter value |
| 3 | Calendar timer alarmvalue |
