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GR551x Datasheet

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Rev.2.6

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文档中心 > GR551x Datasheet/ Peripherals / ISO/IEC 7816-3 Master/ Registers Copy URL

Registers

CTRL

Name: Control Register
Description: This register is only to write.
Base Address: 0xA000F200
Offset: 0x0
Reset Value: 0x00000000

表 250 Control Register
Bits	Field Name	RW	Reset	Description
31	IRQ_TEST_SET	W	0x0	Interrupt Test Set. This register sets test interrupt Value: 0x0: No effect 0x1: Set
30	IRQ_TEST_CLR	W	0x0	Interrupt Test Clear. This register clears test interrupt (has higher priority than ‘IRQ_TEST_SET’) Value: 0x0: No effect 0x1: Clear
29:26	RSVD	W		Reserved bits
25	IRQ_PRESENCE_CLR	W	0x0	Interrupt source presence clear. This register clears interrupt source ‘STAT.IRQ_PRESENCE’. Value: 0x0: No effect 0x1: Clear
24	IRQ_STAT_EC	W	0x0	Interrupt source state_err clear. This register clears interrupt source ‘STAT.IRQ_STAT_ERR’. Value: 0x0: No effect 0x1: Clear
23	IRQ_DMA_EC	W	0x0	Interrupt source dma_err clear. This register clears interrupt source ‘STAT.IRQ_DMA_ERR’. Value: 0x0: No effect 0x1: Clear
22	IRQ_RETYR_EC	W	0x0	Interrupt source retry_err clear. This register clears interrupt source ‘STAT.IRQ_RETYR_ERR’. Value: 0x0: No effect 0x1: Clear
21	IRQ_RX_EC	W	0x0	Interrupt source rx_err clear. This register clears interrupt source ‘STAT.IRQ_RX_ERR’. Value: 0x0: No effect 0x1: Clear
20	IRQ_DONE_CLR	W	0x0	Interrupt source done clear. This register clears interrupt source ‘STAT.IRQ_DONE’. Value: 0x0: No effect 0x1: Clear
19:13	RSVD	W		Reserved bits
12	TX_RETYR_MC	W	0x0	Transmit Retries Maximum Clear. This register clears ‘STAT.TX_RETRY_MAX’. Value: 0x0: No effect 0x1: Clear
11:9	RSVD	W		Reserved bits
8	RX_RETYR_MC	W	0x0	Receive Retries Maximum Clear. This register clears ‘STAT.RX_RETRY_MAX’. Value: 0x0: No effect 0x1: Clear
7:3	RSVD	W		Reserved bits
2:0	ACTION	W	0x0	Value: 0x0: Do Nothing. 0x1: Switch off. 0x2: Stop the clock. 0x3: Switch on and receive ATR. Re-enable clock if clock is stopped. 0x4: Trigger warm reset and receive ATR. 0x5: Receive. 0x6: Transmit. 0x7: Transmit, followed by RX.

STAT

Name: Status Register
Description: This register record interrupt, IO and power status.
Base Address: 0xA000F200
Offset: 0x04
Reset Value: 0x00020000

表 251 Status Register
Bits	Field Name	RW	Reset	Description
31	RSVD	R		Reserved bits
30	IRQ_TEST	R	0x0	Interrupt Test. Test interrupt for connection check. Value: 0x0: No interrupt 0x1: Active
29:26	RSVD	R		Reserved bits
25	IRQ_PRESENCE	R	0x0	Interrupt Presence. SIM card presence changed. Inserted or removed. Value: 0x0: No interrupt 0x1: Active
24	IRQ_STAT_ERR	R	0x0	Interrupt State Error. Action requested while busy or unsupported transition. Value: 0x0: No interrupt 0x1: Active
23	IRQ_DMA_ERR	R	0x0	Interrupt DMA Error. DMA read/write operation could not be issued. Value: 0x0: No interrupt 0x1: Active
22	IRQ_RETRY_ERR	R	0x0	Interrupt Retry Error. Maximum number of retries exceeded. Value: 0x0: No interrupt 0x1: Active
21	IRQ_RX_ERR	R	0x0	Interrupt RX Error. No or incomplete or unexpected data. Value: 0x0: No interrupt 0x1: Active
20	IRQ_DONE	R	0x0	Interrupt Done. Requested operation has been completed. Value: 0x0: No interrupt 0x1: Active
19:18	RSVD	R		Reserved bits
17	PRESENCE_STAT	R	0x1	Status of presence IO. Value: 0x0: Absent 0x1: Presence
16	BUSY	R	0x0	Status of SIM interface. Value: 0x0: Idle 0x1: Busy
15	RSVD	R		Reserved bits
14:12	TX_RETRY_MAX	R	0x0	Transmit Retries Maximum. Maximum number of seen transmit retries after error signaling by SIM.
11	RSVD	R		Reserved bits
10:8	RX_RETRY_MAX	R	0x0	Receive Retries Maximum. Maximum number of seen receive retries after parity error.
7	RSVD	R		Reserved bits
6:4	IO_STAT	R	0x0	IO States. Value: 0x0: IO pin is driven low. 0x1: IO pin is high impedance and driven high by the pull-up. 0x4: Wait for start bit. 0x5: Receive. 0x6: Transmit. 0x7: Wait until next character to ensure configured guard time.
3:0	PWR_STAT	R	0x0	Power States. Value: 0x0: SIM is unpowered. 0x1: Power up SIM. RST asserted (low). Clock stopped. IO is tristate. 0x2: Power up SIM. RST asserted (low). Clock is running. IO is high. 0x3: Power up SIM. RST asserted (low). Clock is running. IO is tristate. 0x4: Power up SIM. RST asserted (low). Clock stopped. IO is low. 0x5: Preparing clock stop. 0x6: Clock stopped. 0x7: Exiting clock stop 0x8: SIM is idle, no communication is ongoing. 0x9: RX TS0 Character. 0xA: RX TS1 Character. 0XB: Receive. 0xC: Transmit. 0xD: Transmit and Receive.

CLK_CFG

Name: Clock Configuration Register
Description: This register configure clock.
Base Address: 0xA000F200
Offset: 0x08
Reset Value: 0x002F0173

表 252 Clock Configuration Register
Bits	Field Name	RW	Reset	Description
31	CLK_STOP_SEL	RW	0x0	Clock Stop Select. Value of the clock output during stopped clock. Value: 0x0: Low 0x1: High
30:24	RSVD	R		Reserved bits
23:16	CLK_DIV	RW	0x2F	Clock Division. Divide system clock by this value + 1.
15:10	RSVD	R		Reserved bits
9:0	ETU_DIV	RW	0x173	Divide SIM clock by this value+1 to define ETU length. The reset value is the one, needed for the ATR.

TIMES_CFG

Name: Times Configuration Register
Description: This register configures the timing
Base Address: 0xA000F200
Offset: 0x10
Reset Value: 0x006B0000

表 253 Times Configuration Register
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R		Reserved bits
29:12	WAIT_TIME	RW	0x6B	Wait time in [ETU]. Maximum card response time (leading edge to leading edge).
11:10	RSVD	R		Reserved bits
9:0	GUARD_TIME	RW	0x0	Guard time in [ETU]. Time between the leading edges of two consecutive characters.

DATA_CFG

Name: Data Configuration Register
Description: This register configures the communication
Base Address: 0xA000F200
Offset: 0x14
Reset Value: 0x00000002

表 254 Data Configuration Register
Bits	Field Name	RW	Reset	Description
31:7	RSVD	R		Reserved bits
6:4	RETRY_LIMIT	RW	0x0	Retries Limit. Maximum number of issued retries before giving up.
3:2	RSVD	R		Reserved bits
1	DETECT_CODING	RW	0x1	Detect Coding Convention. Automatically detect coding convention during ATR reception. Value: 0x0: Disable 0x1: Enable
0	CODING	RW	0x0	Coding Convention. Value: 0x0: Default. High = 1, LSB first. 0x1: Inverse. High = 0, MSB first.

ADDR

Name: Address Register
Description: This register records current address relative to base_addr.
Base Address: 0xA000F200
Offset: 0x18
Reset Value: 0x00000000

表 255 Address Register
Bits	Field Name	RW	Reset	Description
31:20	RSVD	R		Reserved bits
19:2	ADDR	R	0x0	Address. Current address relative to base_addr.
1:0	ADDR_FRAC	R	0x0	Address Fraction. Byte selection.

START_ADDR

Name: Start Address Register
Description: This register configures read/write memory address. RX and TX buffer has to be aligned to 4 bytes, and buffer address [31:2] = START_ADDR[31:2]
Base Address: 0xA000F200
Offset: 0x1c
Reset Value: 0x00000000

表 256 Start Address Register
Bits	Field Name	RW	Reset	Description
31:20	BASE_ADDR	RW	0x0	Base Address. Base Address for RX and TX Buffer.
19:2	START_ADDR	RW	0x0	Start Address. Start address of RX and TX buffer, relative to base_addr.
1:0	RSVD	R		Reserved bits

RX_END_ADDR

Name: RX End Register
Description: This register configures RX data end address
Base Address: 0xA000F200
Offset: 0x20
Reset Value: 0x00000000

表 257 RX End Register
Bits	Field Name	RW	Reset	Description
31:20	RSVD	R		Reserved bits
19:2	RX_END_ADDR	RW	0x0	RX End Address. End address of receive buffer, relative to base_addr.
1:0	RX_END_AF	RW	0x0	RX End Address Fraction. Byte selection.

TX_END_ADDR

Name: TX End Register
Description: This register configures TX data end address
Base Address: 0xA000F200
Offset: 0x24
Reset Value: 0x00000000

表 258 TX End Register
Bits	Field Name	RW	Reset	Description
31:20	RSVD	R		Reserved bits
19:2	TX_END_ADDR	R	0x0	TX End Address. End address of transmit buffer, relative to base_addr.
1:0	TX_END_AF	R	0x0	TX End Address Fraction. Byte selection.

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