GR5515IGND/GR5515IENDU QFN56
Figure 2 shows the pin assignments of GR5515IGND/GR5515IENDU QFN56 package (top view).
Table 2 shows pin descriptions of GR5515IGND/GR5515IENDU QFN56 package.
| Pin # | Pin Name | Pin Type | Description/Default Function | Voltage Domain |
|---|---|---|---|---|
| 1 | VDD_VCO/VDD_RF | Analog/RF supply | Synthesizer VCO supply/RF supply: 1.1 V; connect to VREG. |
|
| 2 | TRX | Analog/RF | RX input and TX output | |
| 3 | VBATT_RF | Analog/RF Supply | Connect to VBATL. | |
| 4 | GPIO_0 | Digital I/O | General purpose I/O; default: SWD_CLK; pad drive level is 2 mA. | VDDIO1 |
| 5 | GPIO_1 | Digital I/O | General purpose I/O; default: SWD_IO; pad drive level is 2 mA. | VDDIO1 |
| 6 | GPIO_2 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 7 | GPIO_3 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 8 | GPIO_4 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 9 | GPIO_5 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 10 | GPIO_6 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 11 | GPIO_7 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 12 | GPIO_8 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 13 | GPIO_9 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 14 | GPIO_10 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 15 | GPIO_11 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 16 | GPIO_12 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 17 | VDDIO_1 | Digital I/O supply | I/O supply voltage. Support external 1.8 V–3.3 V input voltage. | VDDIO1 |
| 18 | GPIO_13 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 19 | GPIO_14 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 20 | GPIO_15 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| 21 | CHIP_EN | Mixed Signal IN | Master Enable for chip reset pin. The high value of CHIP_EN equals VBATL.Minimum value of high level for CHIP_EN is 1 V. |
|
| 22 | VIO_LDO_OUT | PMU | Output of on-chip I/O supply regulator When GR5515IENDU is used and the Flash is supplied at a high voltage, the pin is used as the power input pin of VDDIO0 digital I/O domain by being connected to VBATL |
Connected internally to VDDIO0 |
| 23 | VDD_DIGCORE_1V | PMU | On-chip LDO output for digital core. Connect to a 1 µF capacitor. | |
| 24 | VREG | PMU | Feedback pin from switching regulator | |
| 25 | VSW | PMU | DC-DC converter switching node | |
| 26 | VSS_BUCK | PMU | DC-DC converter supply and general battery GND | |
| 27 | VBATL | PMU | Power supply: 2.2 V to 3.8 V | |
| 28 | RTC_IN | Analog/PMU | Input of inverting amplifier connected to 32.768 kHz crystal | |
| 29 | RTC_OUT | Analog/PMU | Output of inverting amplifier connected to 32.768 kHz crystal | |
| 30 | MSIO4 | Mixed Signal I/O | Configurable to be a GPIO mixed signal (SNSADC interface); pad drive level is 2 mA. | VBATL |
| 31 | MSIO3 | Mixed Signal I/O | Configurable to be a GPIO mixed signal (SNSADC interface); pad drive level is 2 mA. | VBATL |
| 32 | MSIO2 | Mixed Signal I/O | Configurable to be a GPIO mixed signal (SNSADC interface); pad drive level is 2 mA. | VBATL |
| 33 | MSIO1 | Mixed Signal I/O | Configurable to be a GPIO mixed signal (SNSADC interface); pad drive level is 2 mA. | VBATL |
| 34 | MSIO0 | Mixed Signal I/O | Configurable to be a GPIO mixed signal (SNSADC interface); pad drive level is 2 mA. | VBATL |
| 35 | TEST_MODE | Digital I/O | Factory test mode selection pin
|
VDDIO0 |
| 36 | AON_GPIO_0 | Digital I/O | Always-on GPIO | VDDIO0 |
| 37 | AON_GPIO_1 | Digital I/O | Always-on GPIO | VDDIO0 |
| 38 | AON_GPIO_2 | Digital I/O | Always-on GPIO | VDDIO0 |
| 39 | AON_GPIO_3 | Digital I/O | Always-on GPIO | VDDIO0 |
| 40 | AON_GPIO_4 | Digital I/O | Always-on GPIO | VDDIO0 |
| 41 | AON_GPIO_5 | Digital I/O | Always-on GPIO | VDDIO0 |
| 42 | AON_GPIO_6 | Digital I/O | Always-on GPIO | VDDIO0 |
| 43 | AON_GPIO_7 | Digital I/O | Always-on GPIO | VDDIO0 |
| 44 | GPIO_24 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| 45 | GPIO_25 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| 46 | GPIO_16 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| 47 | GPIO_17 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| 48 | GPIO_31 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| 49 | GPIO_30 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| 50 | GPIO_26 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| 51 | GPIO_27 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| 52 | GPIO_28 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| 53 | GPIO_29 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| 54 | VDD_AMS | Analog/RF Supply | AMS supply 1.1 V; connect to VREG. | |
| 55 | XO_OUT | Analog/RF | Output of inverting amplifier connected to 32 MHz crystal | |
| 56 | XO_IN | Analog/RF | Input of inverting amplifier connected to 32 MHz crystal |
