GR5515GGBD BGA55
Figure 5 shows the pin assignments of GR5515GGBD BGA55 package (top view).
Table 5 shows pin descriptions of GR5515GGBD BGA55 package.
| Pin # | Pin Name | Pin Type | Description/Default Function | Voltage Domain |
|---|---|---|---|---|
| A1 | VDD_RF | Analog/RF supply | RF supply: 1.1 V | |
| A2 | VDD_VCO | Analog/RF supply | Synthesizer VCO supply; connect to VREG | |
| A3 | XO_IN | Analog/RF | Input of inverting amplifier connected to 32 MHz crystal | |
| A4 | XO_OUT | Analog/RF | Output of inverting amplifier connected to 32 MHz crystal | |
| A5 | VDD_AMS | Analog/RF supply | AMS supply 1.1 V; connect to VREG | |
| A6 | GPIO30 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| A7 | GPIO25 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| A8 | GPIO26 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| B1 | RF_GND0 | Analog/RF | RF ground | |
| B2 | RF_GND1 | Analog/RF | RF ground | |
| B3 | TPP | Analog/RF | Test Mux + output | |
| B4 | GPIO0 | Digital I/O | General purpose I/O; default: SWD_CLK; pad drive level is 2 mA. | VDDIO1 |
| B5 | GPIO1 | Digital I/O | General purpose I/O; default: SWD_IO; pad drive level is 2 mA. | VDDIO1 |
| B6 | GPIO17 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| B7 | GPIO24 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| B8 | NC | - | - | |
| C1 | TRX | Analog/RF | RX input and TX output | |
| C2 | RF_GND2 | Analog/RF | RF ground | |
| C3 | DGND0 | Digital GND | Digital ground | |
| C4 | DGND1 | Digital GND | Digital ground | |
| C6 | AON_GPIO7 | Digital I/O | Always-on GPIO; pad drive level is 2 mA. | VDDIO0 |
| C7 | AON_GPIO2 | Digital I/O | Always-on GPIO; pad drive level is 2 mA. | VDDIO0 |
| C8 | AON_GPIO5 | Digital I/O | Always-on general purpose I/O | VDDIO0 |
| D1 | VBATT_RF | Analog/RF supply | Connect to VBATL | |
| D2 | GPIO3 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| D7 | MSIO1 | Mixed Signal I/O | Configurable to be a GPIO mixed signal (SNSADC interface); pad drive level is 2 mA. | VBATL |
| D8 | AON_GPIO0 | Digital I/O | Always-on GPIO; pad drive level is 2 mA. | VDDIO0 |
| E1 | GPIO2 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| E2 | GPIO4 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| E7 | MSIO2 | Mixed Signal I/O | Configurable to be a GPIO mixed signal (SNSADC interface); pad drive level is 2 mA. | VBATL |
| E8 | MSIO0 | Mixed Signal I/O | Configurable to be a GPIO mixed signal (SNSADC interface); pad drive level is 2 mA. | VBATL |
| F1 | GPIO5 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| F2 | GPIO6 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| F3 | DGND2 | Digital GND | Digital ground | |
| F4 | TEST_MODE | Digital I/O | Factory test mode selection pin
|
VDDIO0 |
| F5 | AON_GPIO4 | Digital I/O | Always-on GPIO; pad drive level is 2 mA. | VDDIO0 |
| F6 | CHIP_EN | Mixed Signal IN | Master Enable for chip reset pin. The high value of CHIP_EN equals VBATL. |
|
| F7 | MSIO3 | Mixed Signal I/O | Configurable to be a GPIO mixed signal (SNSADC interface); pad drive level is 2 mA. | VBATL |
| F8 | RTC_OUT | Analog/PMU | Output of inverting amplifier connected to 32.768 kHz crystal | |
| G1 | GPIO8 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| G2 | GPIO7 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| G3 | GPIO11 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| G4 | GPIO16 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO0 |
| G5 | VIO_LDO_OUT | Analog/PMU | Output of On-Chip I/O supply regulator | Connected internally to VDDIO0 |
| G6 | VDD_DIGCORE_1V | Analog/PMU | On-chip LDO output for digital core, connected to 1 µF capacitor | |
| G7 | MSIO4 | Mixed Signal I/O | Configurable to be a GPIO mixed signal (SNSADC interface); pad drive level is 2 mA. | VBATL |
| G8 | RTC_IN | Analog/PMU | Input of inverting amplifier connected to 32.768 kHz crystal | |
| H1 | GPIO9 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| H2 | GPIO10 | Digital I/O | General purpose I/O; pad drive level is 2 mA. | VDDIO1 |
| H3 | VDDIO_1 | Digital I/O supply | I/O supply voltage. Support external 1.8 V–3.3 V input voltage. | VDDIO1 |
| H4 | AON_GPIO1 | Digital I/O | Always-on GPIO; pad drive level is 2 mA. | VDDIO0 |
| H5 | VBATL | Analog/PMU | Power supply: 2.2 V to 3.8 V | |
| H6 | VREG | Analog/PMU | Feedback pin of switch regulator | |
| H7 | VSW | Analog/PMU | DC-DC converter switching node | |
| H8 | PMUGND | Analog/PMU | DC-DC converter & general battery GND pin |
