Configuration Principle

The GR5xx SoCs integrate programmable pull-up/pull-down resistors, which can replace external ones to reduce footprint and cost. Additionally, these internal resistors can prevent unused GPIO pins from being floating, thus avoiding unwanted current leakage from the VDDIO power supply.

Follow the principles below to enable/disable the internal pull-up/pull-down resistors of GR5xx SoCs:

1. If a GPIO pin is in floating state, enable the internal pull-up/pull-down resistors.
2. If a GPIO pin is unused, enable the internal pull-down resistor.
3. If a GPIO pin is configured as an input and is pulled up/down by an external device, disable the internal pull-up/pull-down resistors.
4. If a GPIO pin is configured as an input and the connected external device is in high impedance state, enable the internal pull-up/pull-down resistors.
5. If a GPIO pin is configured as an output, disable the internal pull-up/pull-down resistors.
6. A GPIO pin can be configured as an input or output. When the pin is configured as an input, enable the internal pull-up/pull-down resistors if the input level is uncertain.

The circuit of GPIO pins is shown as follows:

The circuit principles are detailed below.

1. If a GPIO pin is in floating state, any external interference voltage on the pin may lead to unintended conduction of the input gate, resulting in excess current flow from VDDIO through the input gate. In this case, enable the internal pull-up/pull-down resistors.
2. If a GPIO pin is configured as an input and is pulled up/down by an external device, disable the internal pull-up/pull-down resistors. Otherwise, current leakage from VDDIO may occur.
   Note:

   However, when the external drive device enters high impedance state, if the internal pull-up/pull-down resistors are not enabled, the GPIO pin will enter floating state, which may cause excess current flow. Therefore, when the external device enters high impedance state, enable corresponding pull-up/pull-down resistors.

   1. If a GPIO pin is used as an input with the pull-up resistor enabled and the connected external device is driving a low level on the pin, current will flow from VDDIO through the pull-up resistor to ground (through the external device), as shown below.

      

      When the pull-up resistor is 100 kΩ (for specific values of the pull-up/pull-down resistors, refer to the corresponding datasheet) and the VDDIO voltage is 3.3 V, if one GPIO pin is configured improperly, there will be excess current leakage (about 33 µA) from VDDIO; if multiple GPIO pins are configured improperly, each pin will have a leakage current of 33 µA.

   2. If a GPIO pin is configured as an input with the pull-down resistor enabled and the connected external device is driving a high level on the pin, then there is no current leakage from VDDIO. However, current will be generated from VDDIO through the external device, as shown below.

      

3. If a GPIO pin is configured as an output, the pull-up/pull-down resistors should be disabled. Otherwise, current leakage may occur and excess current may flow through the enabled pull-up/pull-down resistors.
   1. If a GPIO pin is configured as an output driving high with the pull-down resistor enabled, current flows from VDDIO to the pull-down resistor, as shown below.

      

   2. If a GPIO pin is configured as an output driving low with the pull-up resistor enabled, the leaked current flows through the pull-up resistor and low-level output buffer to ground, as shown below.