Macros
SCLK Gate
Peripheral Driver » LL Driver » I2S » Defines » I2S Exported Constants

Macros

#define LL_I2S_SCLKG_NONE   (0x00000000UL)
 
#define LL_I2S_SCLKG_CYCLES_12   (0x1UL << I2S_CLKCONFIG_SCLKG_Pos)
 
#define LL_I2S_SCLKG_CYCLES_16   (0x2UL << I2S_CLKCONFIG_SCLKG_Pos)
 
#define LL_I2S_SCLKG_CYCLES_20   (0x3UL << I2S_CLKCONFIG_SCLKG_Pos)
 
#define LL_I2S_SCLKG_CYCLES_24   (0x4UL << I2S_CLKCONFIG_SCLKG_Pos)
 

Detailed Description

Macro Definition Documentation

◆ LL_I2S_SCLKG_CYCLES_12

#define LL_I2S_SCLKG_CYCLES_12   (0x1UL << I2S_CLKCONFIG_SCLKG_Pos)

Gating after 12 sclk cycles.

◆ LL_I2S_SCLKG_CYCLES_16

#define LL_I2S_SCLKG_CYCLES_16   (0x2UL << I2S_CLKCONFIG_SCLKG_Pos)

Gating after 16 sclk cycles.

◆ LL_I2S_SCLKG_CYCLES_20

#define LL_I2S_SCLKG_CYCLES_20   (0x3UL << I2S_CLKCONFIG_SCLKG_Pos)

Gating after 20 sclk cycles.

◆ LL_I2S_SCLKG_CYCLES_24

#define LL_I2S_SCLKG_CYCLES_24   (0x4UL << I2S_CLKCONFIG_SCLKG_Pos)

Gating after 24 sclk cycles.

◆ LL_I2S_SCLKG_NONE

#define LL_I2S_SCLKG_NONE   (0x00000000UL)

Clock gating is disabled.