GPIO

Introduction

A GR5526 SoC has up to 34 individually configurable GPIOs that can serve as peripherals or digital input/output.

Main Features

Up to 34 digital GPIOs: GPIO_0–GPIO_15 are supplied by VDDIO_1. GPIO_16–GPIO_33 are supplied by VDDIO_0.
All I/Os except GPIO_10–GPIO_25, GPIO_32, and GPIO_33 can retain their output levels when the system enters sleep mode.
GPIO default state is input mode with pull-down.
All GPIOs can be configured as being triggered by high level, low level, rising edge, falling edge, or both edges.

Functional Description

The 34 digital GPIOs can be used:

For general-purpose input/output.
To multiplex different peripherals on different output pins of the package.
To multiplex debug signals from different blocks of the GR5526 SoC.

A functional drawing of the GPIO pads is provided in 图 22. The digital GPIO pads can be configured to set direction, enable pull-up/pull-down resistors, and enable output retention. GPIOs can also be read or written by firmware for applications that need direct access through the GPIOx registers.

The general rule for enabling the on-chip pull-up/pull-down resistors is as follows:

If a GPIO is unused, enable a pull-down resistor.
If a GPIO is configured as an output, disable the pull-up/pull-down resistor. However, if disabling the output causes a high impedance state, enable the pull-up or pull-down resistor during this period.
If a GPIO is used as an input and is being actively driven high or low by an external device, disable the pull-up/pull-down resistor (the same thing goes when there is an external pull-up/pull-down resistor on the board. In this case, the on-chip resistor should always be disabled). However, if the external device driving the input ever goes to a high impedance state, a pull-up or pull-down resistor must be enabled during this period.

Note:

GPIO_10–GPIO_25 become high impedance in sleep and cannot retain their output levels. During sleep, the signal level of these IOs is determined by the pull-up/pull-down resistors.

Registers

DPAD_R_EN_BUS_0

Name: GPIO Pull-Up/Down Resistor Enable Register
Description: This register decides whether to use pull-up/down resistors.
Base Address: 0x4000EE00
Offset: 0x000
Reset Value: 0x00000000

表 145 DPAD_R_EN_BUS_0 Register
Bits	Field Name	RW	Reset	Description
31:0	DPAD_R_EN	RW	0x0	Resistor enable control of GPIO_31–GPIO_0 Value: 0x0: Enable pull-up/down resistor. 0x1: Disable pull-up/down resistor.

DPAD_RTYP_BUS_0

Name: GPIO Resistor Type Control Register
Description: This register sets the resistor type to either pull-up or pull-down.
Base Address: 0x4000EE00
Offset: 0x004
Reset Value: 0x00000000

表 146 DPAD_RTYP_BUS_0 Register
Bits	Field Name	RW	Reset	Description
31:0	DPAD_RTYP	RW	0x0	Resistor type of GPIO_31–GPIO_0 Value: 0x0: Pull down. 0x1: Pull up.

DPAD_IN_EN_BUS_0

Name: GPIO Input Enable Register
Description: This register enables a GPIO as input.
Base Address: 0xA000E000
Offset: 0x008
Reset Value: 0x00000000

表 147 DPAD_IN_EN_BUS_0 Register
Bits	Field Name	RW	Reset	Description
31:0	DPAD_IN_EN	RW	0x0	Active l/O inputs to GPIO_31–GPIO_0 Value: 0x0: Enable inputs to pad. 0x1: Disable inputs to pad.

DPAD_R_EN_BUS_1

Name: GPIO Pull-Up/Down Resistor Enable Register
Description: This register decides whether to use pull-up/down resistors.
Base Address: 0x4000EE00
Offset: 0x000
Reset Value: 0x00000000

表 148 DPAD_R_EN_BUS_1 Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R		Reserved bits
1:0	DPAD_R_EN	RW	0x0	Resistor enable control of GPIO_33–GPIO_32. Value: 0x0: Enable pull-up/down resistor. 0x1: Disable pull-up/down resistor.

DPAD_RTYP_BUS_1

Name: GPIO Pull-Up/Down Resistor Type Control Register
Description: This register sets the resistor type to either pull-up or pull-down.
Base Address: 0x4000EE00
Offset: 0x004
Reset Value: 0x00000000

表 149 DPAD_RTYP_BUS_1 Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R		Reserved bits
1:0	DPAD_RTYP	RW	0x0	Resistor type of GPIO_33–GPIO_32 Value: 0x0: Pull down. 0x1: Pull up.

DPAD_IN_EN_BUS_1

Name: GPIO Input Enable Register
Description: This register enables a GPIO as input.
Base Address: 0x4000E000
Offset: 0x008
Reset Value: 0x00000000

表 150 DPAD_IN_EN_BUS_1 Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R		Reserved bits
1:0	DPAD_IN_EN	RW	0x0	Active l/O inputs to the GPIO_33 – GPIO_32 Value: 0x0: Enable inputs to pad. 0x1: Disable inputs to pad.

DPAD_R_EN_MISC

Name: OSPI and XQSPI I/O Pull-Up/Down Resistor Enable Register
Description: This register decides whether to use pull-up/down resistors.
Base Address: 0x4000EE00
Offset: 0x000
Reset Value: 0x00000000

表 151 DPAD_R_EN_MISC Register
Bits	Field Name	RW	Reset	Description
31:22	RSVD	R		Reserved bits
21:18	xqspi_io	RW	0x0	Value: 0x0: Enable pull-up/down resistor for XQSPI I/O. 0x1: Disable pull-up/down resistor for XQSPI I/O.
17	xqspi_cs	RW	0x0	Value: 0x0: Enable pull-up/down resistor for XQSPI CS. 0x1: Disable pull-up/down resistor for XQSPI CS.
16	xqspi_clk	RW	0x0	Value: 0x0: Enable pull-up/down resistor for XQSPI clk. 0x1: Disable pull-up/down resistor for XQSPI clk.
15:11	RSVD	R		Reserved bits
10:3	ospi_io	RW	0x0	Value: 0x0: Enable pull-up/down resistor for OSPI I/O. 0x1: Disable pull-up/down resistor for OSPI I/O.
2	ospi_cs	RW	0x0	Value: 0x0: Enable pull-up/down resistor for OSPI CS. 0x1: Disable pull-up/down resistor for OSPI CS.
1	ospi_dqs	RW	0x0	Value: 0x0: Enable pull-up/down resistor for OSPI DQS. 0x1: Disable pull-up/down resistor for OSPI DQS.
0	ospi_clk	RW	0x0	Value: 0x0: Enable pull-up/down resistor for OSPI clk. 0x1: Disable pull-up/down resistor for OSPI clk.

DPAD_RTYP_MISC

Name: OSPI and XQSPI Pull-Up/Down Resistor Type Control Register
Description: This register sets the resistor type to either pull-up or pull-down.
Base Address: 0x4000EE00
Offset: 0x004
Reset Value: 0x003F0000

表 152 DPAD_RTYP_MISC Register
Bits	Field Name	RW	Reset	Description
31:22	RSVD	R		Reserved bits
21:18	xqspi_io	RW	0x0	Value: 0x0: Pull down. 0x1: Pull up.
17	xqspi_cs	RW	0x0	Value: 0x0: Pull down. 0x1: Pull up.
16	xqspi_clk	RW	0x0	Value: 0x0: Pull down. 0x1: Pull up.
15:11	RSVD	R		Reserved bits
10:3	ospi_io	RW	0x0	Value: 0x0: Pull down. 0x1: Pull up.
2	Ospi_cs	RW	0x0	Value: 0x0: Pull down. 0x1: Pull up.
1	ospi_dqs	RW	0x0	Value: 0x0: Pull down. 0x1: Pull up.
0	ospi_clk	RW	0x0	Value: 0x0: Pull down. 0x1: Pull up.

DPAD_IN_EN_MISC

Name: OSPI and XQSPI Pin Input Enable Register
Description: This register enables the input.
Base Address: 0x4000E000
Offset: 0x008
Reset Value: 0x00000000

表 153 DPAD_IN_EN_MISC Register
Bits	Field Name	RW	Reset	Description
31:22	RSVD	R		Reserved bits
21:18	xqspi_io	RW	0x0	Value: 0x0: Enable inputs to pad for XQSPI I/O. 0x1: Disable inputs to pad for XQSPI I/O.
17	xqspi_cs	RW	0x0	Value: 0x0: Enable inputs to pad for XQSPI CS. 0x1: Disable inputs to pad for XQSPI CS.
16	xqspi_clk	RW	0x0	Value: 0x0: Enable inputs to pad for XQSPI clk. 0x1: Disable inputs to pad for XQSPI clk.
15:11	RSVD	R		Reserved bits
10:3	ospi_io	RW	0x0	Value: 0x0: Enable inputs to pad for OSPI I/O. 0x1: Disable inputs to pad for OSPI I/O.
2	ospi_cs	RW	0x0	Value: 0x0: Enable inputs to pad for OSPI CS. 0x1: Disable inputs to pad for OSPI CS.
1	ospi_dqs	RW	0x0	Value: 0x0: Enable inputs to pad for OSPI DQS. 0x1: Disable inputs to pad for OSPI DQS.
0	ospi_clk	RW	0x0	Value: 0x0: Enable inputs to pad for OSPI clk. 0x1: Disable inputs to pad for OSPI clk.

GPIOx_DATA

Name: GPIO Data Value Register
Description: This register contains the input data and can write it to data output register.
Base Address: 0x40010000 + x*0x1000
Offset: 0x0000
Reset Value: 0x00000000

表 154 GPIOx_DATA Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	DATA	RW	0x0	Data value [15:0]: Read: Read the value that is sampled at pin Write: Write the field to the GPIOx_DATA_OUT register.

Note:

GPIOx includes GPIOA (GPIO_0–GPIO_15), GPIOB (GPIO_16–GPIO_31), and GPIOC (GPIO_32–GPIO_33).

GPIOx_DATA_OUT

Name: GPIO Data Output Register
Description: This register contains the output data.
Base Address: 0x40010000 + x*0x1000
Offset: 0x0004
Reset Value: 0x00000000

表 155 GPIOx_DATA_OUT Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	DATA_OUT	RW	0x0	Data output register value [15:0]: Read: current value of data output register Write: to data output register

GPIOx_OUT_EN

Name: GPIO Output Enable Register
Description: This register is used to enable the GPIO as output.
Base Address: 0x40010000 + x*0x1000
Offset: 0x0010
Reset Value: 0x00000000

表 156 GPIOx_OUT_EN Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	EN	RW	0x0	Output enable set [15:0]: Read: 0x0: As input 0x1: As output Write: 0x0: No effect 0x1: Set the output enable bit.

GPIOx_OUT_CLR

Name: GPIO Output Enable Clear Register
Description: This register is used to disable output bit.
Base Address: 0x40010000 + x*0x1000
Offset: 0x0014
Reset Value: 0x00000000

表 157 GPIOx_OUT_CLR Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	CLR	RW	0x0	Output enable clear [15:0]: Read: 0x0: as input 0x1: as output Write: 0x0: No effect 0x1: Clear the output enable bit.

GPIOx_INT_EN

Name: GPIO Interrupt Enable Register
Description: This register is used to enable GPIO interrupt.
Base Address: 0x40010000 + x*0x1000
Offset: 0x0020
Reset Value: 0x00000000

表 158 GPIOx_INT_EN Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	EN	RW	0x0	Interrupt enable set [15:0]: Read: 0x0: Interrupt disabled 0x1: Interrupt enabled Write: 0x0: No effect 0x1: Set the interrupt enable bit.

GPIOx_INT_CLR

Name: GPIO Interrupt Enable Clear Register
Description: This register is used to disable GPIO interrupt.
Base Address: 0x40010000 + x*0x1000
Offset: 0x0024
Reset Value: 0x00000000

表 159 GPIOx_INT_CLR Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	CLR	RW	0x0	Interrupt enable clear [15:0]: Read: 0x0: Interrupt disabled 0x1: Interrupt enabled Write: 0x0: No effect 0x1: Clear the interrupt enable bit.

GPIOx_INT_TYPE_EN

Name: GPIO Interrupt Type Enable Register
Description: This register is used to set GPIO interrupt type.
- Interrupt type is 0 and interrupt polarity is 0: low-level trigger interrupt
- Interrupt type is 0 and interrupt polarity is 1: high-level trigger interrupt
- Interrupt type is 1 and interrupt polarity is 0: falling edge trigger interrupt
- Interrupt type is 1 and interrupt polarity is 1: rising edge trigger interrupt

Base Address: 0x40010000 + x*0x1000
Offset: 0x0028
Reset Value: 0x00000000

表 160 GPIOx_INT_TYPE_EN Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	EN	RW	0x0	Interrupt type set [15:0]: Read: 0x0: Low or high level 0x1: Falling edge or rising edge Write: 0x0: No effect 0x1: Set the interrupt type bit.

GPIOx_INT_TYPE_CLR

Name: GPIO Interrupt Type Clear Register
Description: This register is used to disable GPIO interrupt type.
Base Address: 0x40010000 + x*0x1000
Offset: 0x002C
Reset Value: 0x00000000

表 161 GPIOx_INT_TYPE_CLR Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	CLR	RW	0h 0	Interrupt type clear [15:0]: Read: 0x0: Low or high level 0x1: Falling edge or rising edge Write: 0x0: No effect 0x1: Clear the interrupt type bit.

GPIOx_INT_POL_EN

Name: GPIO Interrupt Polarity Enable Register
Description: This register is used to enable GPIO interrupt polarity.
Base Address: 0x40010000 + x*0x1000
Offset: 0x0030
Reset Value: 0x00000000

表 162 GPIOx_INT_POL_EN Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	EN	RW	0h 0	Polarity configuration [15:0]: Read: 0x0: Low level or falling edge 0x1: High level or rising edge Write: 0x0: No effect 0x1: Set the interrupt polarity bit.

GPIOx_INT_POL_CLR

Name: GPIO Interrupt Polarity Disable Register
Description: This register is used to disable GPIO interrupt polarity.
Base Address: 0x40010000 + x*0x1000
Offset: 0x0034
Reset Value: 0x00000000

表 163 GPIOx_INT_POL_CLR Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	CLR	RW	0x0	Polarity configuration [15:0]: Read: 0x0: Low level or falling edge 0x1: High level or rising edge Write: 0x0: No effect 0x1: Clear the interrupt polarity bit.

GPIOx_INT_STAT

Name: GPIO IRQ Status Register
Description: This register contains GPIO interrupt status and is used to clear the interrupt request.
Base Address: 0x40010000 + x*0x1000
Offset: 0x0038
Reset Value: 0x00000000

表 164 GPIOx_INT_STAT Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	STAT_CLR	RW	0x0	Write one to clear interrupt request: Read: [15:0] IRQ status register Write: 0x0: No effect 0x1: To clear the interrupt request

Electrical Specifications

The electrical parameters for the GPIO_0–GPIO_33 are as follows:

表 165 GPIO electrical specifications
Parameter	Description	Min.	Typ.	Max.	Unit
V_IH	Input high voltage	VDDIO x 0.7		VDDIO	V
V_IL	Input low voltage	VSSIO		VDDIO x 0.3	V
V_OH,L	Output high voltage, 4 mA, VDDIO ≥ 1.7 V	VDDIO – 0.4		VDDIO	V
V_OH,M	Output high voltage, 4 mA, VDDIO ≥ 2.5 V	VDDIO – 0.4		VDDIO	V
VOH,H	Output high voltage, 4 mA, VDDIO ≥ 3 V	VDDIO – 0.4		VDDIO	V
V_OL,L	Output low voltage, 4 mA, VDDIO ≥1.7 V	VSS		VSS + 0.4	V
V_OL,M	Output low voltage, 4 mA, VDDIO ≥ 2.5 V	VSS		VSS + 0.4	V
VOL,H	Output low voltage, 4 mA, VDDIO ≥ 3 V	VSS		VSS + 0.4	V
I_OL,L	Current at VSS+0.4 V, output set low, VDDIO ≥1.7 V			4	mA
I_OL,M	Current at VSS+0.4 V, output set low, VDDIO ≥ 2.5 V			5	mA
I_OH,L	Current at VDD-0.4 V, output set high, VDDIO ≥ 1.7 V			4	mA
I_OH,M	Current at VDD-0.4 V, output set high, VDDIO ≥ 2.5 V			5	mA
t_RF,15pF	Rise/Fall time, 10% – 90%, 15 pF load		5	8	ns
t_RF,25pF	Rise/Fall time, 10% – 90%, 25 pF load		6	13	ns
R_PU	Pull-up resistance	70	120	150	kΩ
R_PD	Pull-down resistance	70	120	150	kΩ
C_PAD	Pad capacitance		5		pF