eFuse

Introduction

GR5526 eFuse (512 bytes) stores the product ID, TRIM, and security parameters. It consists of Main Region (240 bytes), Backup Region (240 bytes), and User Region (32 bytes). User Region is reserved for users to write and read data by calling the eFuse driver. Every single byte of eFuse can only be written once. 图 7 shows the structure of eFuse.

Note:

The access to eFuse should be word-aligned, which means the offset address can only be 0x0, 0x4, …, 0x1C.

Main Features

The initial eFuse bit is zero, and it can only be changed once from zero to one.
Little-endian mode; the minimum unit size of read or write is 4 bytes.
The Main Region has three sections: Key section, Control section and TRIM section0.
- Key section stores all the keys needed for Secure Boot and SPI Flash encryption.
- Control section stores some parameters required by the boot loader for chip configuration.
- TRIM section0 stores chip UID, TRIM parameters, and product configurations. Users can read the chip UID from the address 0x40016110.
The Backup Region has three sections: Key section, Control section and TRIM section1.
- The values in Control section and Key section of the Backup Region are the same as those in the Main Region.
- TRIM section1 is used to save Flash parameters as well as ADC and COMP calibration parameters.
The User Region is reserved for users to write and read data by calling the eFuse driver.
- The base address of User Region is 0x40016000.
- Every single byte of eFuse can only be written once.
- Reading from or writing to User Region requires disabling main_or_backup.

Users can use GProgrammer to create and download eFuse files.

eFuse Information

表 10 eFuse information
Name	Offset	Size (Byte)	Description
Product ID	0x15E	0x2	Product ID; the default value is 0x0000; customers can write this field.
Chip ID	0x158	0x6	Chip ID; the default value is 0x000000000000; customers can write this filed.
EncMode	0x152	0x2	Firmware security mode (encryption and signature verification) 0000 0000b: Firmware normal mode Others: Firmware security mode
SWDDisable	0x150	0x2	Bit0–Bit15: Disable SWD. 0000 0000b: SWD enabled Others: SWD disabled
Config	0x14C	0x4	Bit0: In-system programming (ISP) process by UART 0b: UART ISP process is supported. 1b: UART ISP process is not supported. Bit1: ISP process by USB 0b: USB ISP process is supported. 1b: USB ISP Process is not supported. Bit2: ISP process by J-Link 0b: J-Link ISP process is supported. 1b: J-Link ISP process is not supported. Bit3–Bit5: In security mode, system clock frequency during cold boot 000b: XO 16 MHz 001b: PLL 64 MHz 010b: PLL 96 MHz 011b: PLL 48 MHz 100b: PLL 24 MHz 101b: PLL 16 MHz Bit6–Bit8: In security mode, XQSPI clock frequency during cold boot 000b: 16 MHz 001b: 48 MHz 010b: 32 MHz 011b: 24 MHz 100b: 16 MHz 101b: 64 MHz Bit9–Bit16: XQSPI XIP read mode 0000 0011b: Read mode 0000 1011b: Fast read mode 0011 1011b: DualOut fast read mode 0110 1011b: QuadOut fast read mode 1011 1011b: DualIO fast read mode 1110 1011b: QuadIO fast read mode Bit17: Memory size 0b: 512 KB 1b: 288 KB Bit18–Bit31: Reserved
Package Type	0x134	0x2	Bit0–Bit4: Chip type 0x0100: GR5526VGBIP 0x0101: GR5526VGBI 0x0200: GR5526RGNIP 0x0201: GR5526RGNI Others: Reserved
XO	0x12A	0x2	Bit0-Bit15: XO offset
BT_MAC	0x124	0x6	Bluetooth device address; the system will find the address in NVDS (Non-Volatile Data Storage) first; if no address is found in NVDS, then use this address as the device address.
IO_LDO_SEL	0x123	0x1	Bit0: IO_LDO selector 0b: LDO voltage is 1.8 V. 1b: LDO voltage is 3.3 V. Bit1: IO_LDO bypass 0b: bypass disabled 1b: bypass enabled
Chip UUID	0x110	0x10	Byte0–Byte2: FAB Byte3: Year Byte4: Month Byte5–Byte12: LOT_ID Byte13: Wafer_ID Byte14: Wafer_X Byte15: Wafer_Y
User region	0x000	0x20	eFuse user region; customers can write this field.

Registers

EFUSE_TPGM

Name: EFUSE TPGM Register
Description: EFUSE TPGM Register
Base Address: 0x4001_6400
Offset: 0x00
Reset Value: 0x100000F0

表 11 EFUSE_TPGM Register
Bits	Field Name	RW	Reset	Description
31:24	EFUSE_WR_INR	RW	0x10	Interval between two bits in eFuse, number of APB CLK cycles
11:0	EFUSE_PGM_T	RW	0xF0	eFuse program time, tpro = EFUSE_PGM_T*T, where T is clock period; range: 9000 ns < tpro < 11000 ns (typical: 10000 ns)

EFUSE_PGENB

Name: EFUSE PGENB Register
Description: EFUSE PGENB Register
Base Address: 0x4001_6400
Offset: 0x04
Reset Value: 0x00000001

表 12 EFUSE PGENB Register
Bits	Field Name	RW	Reset	Description
0	PGENB	RW	0x1	eFuse PGENB signal

EFUSE_OPTION

Name: EFUSE OPTION Register
Description: EFUSE OPTION Register
Base Address: 0x4001_6400
Offset: 0x08
Reset Value: 0x00000000

表 13 EFUSE OPTION Register
Bits	Field Name	RW	Reset	Description
0	EFUSE_INIT_CHK_START	WO	0x0	Writing "1" to this bit enables eFuse ctrl to start to read the whole eFuse value; writing “0” to this bit enables checking this value.

EFUSE_STAT

Name: EFUSE STAT Register
Description: EFUSE STAT Register
Base Address: 0x4001_8400
Offset: 0x10
Reset value: 0x00000000

表 14 EFUSE STAT Register
Bits	Field Name	RW	Reset	Description
2	EFUSE_WR_DONE	RC	0x0	1: eFuse one word write done Note: Reading this register enables hardware to clear this bit.
1	EFUSE_INIT_CHK_OK	RC	0x0	1: eFuse initial value check success which means the eFuse values are all "0" Note: Reading this register enables hardware to clear this bit.
0	EFUSE_INIT_CHK_DONE	RC	0x0	1: eFuse initial value check done Note: Reading this register enables hardware to clear this bit.

RF_REG_2

Name: RF_REG_2 Register
Description: RF_REG_2 Register
Base Address: 0x4000A800
Offset: 0x0C
Reset Value: 0x0000A0C0

表 15 RF_REG_2 Register
Bits	Field Name	RW	Reset	Description
12	EFUSE_VDDQ_EN_DLY	RW	0x0	Delayed enable signal for efuse_vddq (2.5 V)
11	EFUSE_VDDQ_EN	RW	0x0	Enable eFuse 2.5 V.
10	EFUSE_VDD_EN	RW	0x0	Enable eFuse 1.1 V.