13-Bit SADC
Introduction
The Sense Analog-to-Digital Converter (SADC) is an ADC based on successive approximation registers (SARs). It is an 8-sensing-channel 13-bit 1 Msps ADC that can be used for single ended or for differential measurements. The SADC supports DMA to allow for large sample collection without overloading the MCU.
Main Features
- 13-bit analog-to-digital conversion
- 8-channel (MSIO_0–MSIO_7) analog-to-digital conversion
- Up to 16 MHz ADC clock frequency
- Up to 1 Msps conversion rate
- Programmable ADC sampling clock
- Single-ended or differential measurements
- Internal temperature and Vbattery sensors
- Ability to capture ADC samples using DMA, unburdening the MCU.
- Programmable internal reference
Block Diagram
Resource Sharing
ADC and Comp can share the input channel from MSIO, but MSIO selected for Comp cannot be used at the same time for ADC sampling. The selection and configuration of IO can be found in the Pin Mux and I/O section.
Functional Description
The SADC can sample one of 8 analog sources at a given time, using an input mux. Another two of the channel_N are used internally for VBAT and temperature monitoring for adjusting the analog and RF circuitry configurations for optimum performance. SADC can be reconfigured to perform single-ended or differential measurements through CFG.MODE register. The reference voltage can be internally generated or supplied as one of the external inputs and can be selected through CFG.REF_SEL register. The external reference source can be input through MSIO_0–MSIO_3, and the input voltage must not exceed one half of the supply voltage. The internal reference voltage can be programmed as 0.8 V, 1.2 V, 1.6 V, and 2.0 V through CFG.BIAS_RES_CTRL register. Affected by ambient temperature and chip manufacturing process, the internal reference voltage will have a maximum error of 20%. For any specific reference value (Vref), the maximum ADC input is supposed to be (2 x Vref). As shown in the following figure, the Iref comes from the relatively constant current generated by the chip's bandgap module and will not be affected by other modules; it will generate different Vref levels by resistive voltage division.
The ADC sampling clock can be configured as 16 kHz, 8 kHz, 4 kHz, 16 MHz, 8 MHz, 4 MHz, or 1 MHz through CLK.CLK_SEL register. The output value of the ADC will be stored into the FIFO, and users can transfer the data to RAM through DMA or MCU.
SADC Raw Data Stream
- Pairs of successive 13-bit samples from SADC are combined into 32-bit words by aligning the 16-bit samples. 32-bit words are stored into an SADC FIFO of 64 entries, where each entry is 32-bit long and would hold 2 samples.
- When the SADC FIFO entry count reaches the 6-bit threshold value specified in the FIFO_CTRL.THD register, the samples stored in the FIFO are automatically streamed to the SRAM by using DMA controller. (DMA0 assigned to SADC must be programmed accordingly).
- The SADC FIFO status (not-empty signal and the entry count) can be polled in the FIFO_STAT register.
- The SADC FIFO can also be “popped” by one entry, by reading the FIFO_RD register.
SADC Sample Operation Mode
The SADC supports two sample operation modes: single-end measurement mode and differential measurement mode. Users can choose either of the modes by programming MODE bit of CFG.MODE register.
- In single-end measurement mode, the input signal should be assigned to channel N and the SADC will only measure the input signal of channel N. In this mode, larger voltage input indicates smaller raw data output. The input signal of channel N can be selected as MSIO_0–MSIO_7, temperature sensor, battery voltage, or internal reference voltage by configuring the CFG.CH_N register. The raw data of the output is the measurement from N channel to GND and the allowed range of channel N is 0 to 2*Vref.
- In differential measurement mode, the input signals should be assigned to channel P and channel N and the SADC will measure the input signal of channel P minus channel N. The input signal of channel N is the same with that in single-end measurement mode, and the input signal of channel P can be selected as MSIO_0–MSIO_7 or internal reference voltage by configuring the CFG.CH_P register. The raw data of the output is the measurement of difference voltage between channel P to channel N and the allowed range of channel P minus channel N is -2*Vref to 2*Vref.
When users want to get the temperature sensor voltage, battery voltage, or internal reference voltage, only single-ended measurement mode can be selected.
SADC Clock and Sampling Rate
- The SADC supports both fast sampling and slow sampling. If you need fast sampling, you can select 1M, 4M, 8M, or 16M ADC clock frequency. If you need slow sampling, you can select 16K, 8K, or 4K ADC clock frequency. The SADC clock can be selected by configuring CLK.CLK_SEL register. The source of the SADC clock is shown in the figure below.
图 142 Source of SADC clock - It takes 2 clocks for the SADC to sample and hold data, and then 13 clocks to convert analog semaphore to 13-bit binary digits, totaling 15 clocks to generate one code. Therefore, the sampling rate of the SADC is 1/15 of the ADC clock frequency. For example, a 1 MHz ADC clock has a sampling rate of 66.7 ksps.
- The ADC sampling capacitor is 2 pF, which is affected by the RC circuit. If the external impedance is larger, the charging time of the capacitor will be longer. When a higher SADC sampling rate is set, it is likely to get abnormal raw data during sampling, because the capacitor is not fully charged. This can be solved by reducing the external impedance or reducing the SADC sampling rate.
Considerations for Using SADC
When using an internal reference source, it is necessary for users to ensure the stability of the reference source. The internal reference voltage is divided by the chip power supply voltage, so the reference source voltage of different levels has certain requirements for the chip power supply voltage. Insufficient chip supply voltage will lead to great ADC measurement error. The chip supply voltage range corresponding to the reference sources of different gears is as follows:
Internal Reference | Chip Supply Voltage |
---|---|
0.8 V | 1.8 V to 4.35 V |
1.2 V | 2.6 V to 4.35 V |
1.6 V | 3.2 V to 4.35 V |
2.0 V | 4.0 V to 4.35 V |
For the first data acquisition after SADC initialization, the SADC module needs to spend a cycle to clear the previous sampling parameters and another cycle to make the new sampling parameters effective. Therefore, when starting the SADC for the first time, the results of the first 2 to 3 pieces of 13-bit data may be unstable. It is recommended to filter out the first 2 to 3 pieces of unstable 13-bit data after SADC starts working.
Measuring MSIO Input
Due to the offset of the ADC itself, the original value of 0–8191 cannot accurately correspond to the voltage of 0–2*Vref, so the ADC of each chip needs to be calibrated. Usually, the slope and offset of the straight line are obtained by the method of linear fitting, and the current voltage can be converted by substituting the raw data.
-
In the final test stage, the slope_int_0p8 and offset_int_0p8 of the 0.8 V internal reference voltage are obtained by measuring the two input voltages and their corresponding raw data, and the slope_int_0p8 and offset_int_0p8 are stored in the eFuse (refer to eFuse). You can use the following formula to convert the raw data into the current voltage value.
Similarly, eFuse also stores slope_int_1p2, offset_int_1p2 of the 1.2 V internal reference voltage, and slope_int_1p6, offset_int_1p6 of the 1.6 V internal reference voltage. When the internal 1.2 V reference voltage is selected, the raw data can be converted into the current voltage value by the following formula:
When the internal 1.6 V reference voltage is selected, the raw data can be converted into the current voltage value by the following formula:
- The slope_ext_1p0 and offset_ext_1p0 of the external 1.0 V reference source are also stored in the eFuse. When the external reference voltage is selected, you only need to pay attention to the scaling of the slope_ext_1p0. The conversion formula is as follows:
The above conversion formulas are used when the single-ended mode is selected. If the differential mode is selected, the slope here will be reduced to one-half.
Measuring Battery Voltage
There is a voltage divider resistor inside the GR5526 to divide the voltage of the battery as VBATL/4. Users need to configure the CFG.CH_N register as 0xE (battery sensor as input), and select the internal reference voltage of 0.8 V.
Therefore, users can obtain the raw data of the current voltage, and then convert the raw data into the actual battery voltage value through the following formula:
Where, slope_int_0p8 and offset_int_0p8 are calibration offset and slope when 0.8 V internal reference voltage is selected; 3.854 represents the divider ratio of the resistor to the battery voltage. With the change of temperature, this divider ratio will be slightly different, ranging from 3.85 to 3.855; the typical value is 3.854.
Measuring Internal Temperature
GR5526 has a temperature sensor module inside, and the measurement range is from -40°C to 80°C. The temperature sensor converts the internal temperature of the chip into a voltage value as Vtemp and outputs it to the ADC for sample and conversion. After temperature calibration, the ADC converts the raw data into an actual temperature value.
If users want to measure the internal temperature of the chip, it is necessary to configure the CFG.CH_N register as 0xD (temperature sensor as input), and select the internal reference voltage of 0.8 V. The calibration formula is as follows:
Where, temp_25 represents an ambient temperature of 25°C; temp_25_offset represents ADC raw data at 25°C ambient temperature; slope_int_0p8 represents the calibrated slope value of the internal 0.8 V reference voltage; -0.00175 represents the amplification factor for the slope when used to measure temperature. In general, the output voltage decreases by a typical value of 1.863 mV for every 1 degree increase in temperature. The typical value of the voltage is 807.5 mV at -40°C and 583.9 mV at 80°C.
SADC Manual Calibration Method
Although we have provided some calibration values stored in the eFuse at 3.3 V supply and normal temperature, these calibration values may have errors at other ambient temperatures. Users can use the following methods to recalibrate the conversion relationship between raw data and actual temperature or voltage.
- Single-ended mode calibration with internal reference source
- Select internal reference source by configuring the CFG.REF_SEL register, select internal reference level by configuring the CFG.BAIS_RES_CTRL register, and select single-ended mode by configuring the CFG.MODE register to initialize ADC.
- Use a noise-free power supply to connect to the N terminal by configuring the CFG.CH_N register to start ADC sampling.
- Sample 1024 pieces of data and remove the maximum and minimum values to obtain the average of 1022 numbers.
- At this time, the average value is recorded as x0, and the input voltage is recorded as y0.
- Collect another voltage value using the above method, record the average code value as x1, and record the input voltage value as y1.
- Use the formula , and bring in x0, y0, x1, y1 to obtain the offset and slope.
- The raw data can be converted into the actual voltage using the following formula:
- Differential-ended mode calibration with internal reference source
- Select internal reference source by configuring the CFG.REF_SEL register, select internal reference level by configuring the CFG.BAIS_RES_CTRL register, and select differential-ended mode by configuring the CFG.MODE register to initialize ADC.
- Use two noise-free power supplies to connect to the P terminal and N terminal by configuring the CFG.CH_P register and the CFG.CH_N register to start ADC sampling.
- Sample 1024 pieces of data and remove the maximum and minimum values to obtain the average of 1022 numbers.
- At this time, the average value is recorded as x0, and the value of the P terminal voltage minus the N terminal voltage is recorded as y0.
- Collect another voltage value using the above method, record the average code value as x1, and record the input voltage difference as y1.
- Use the formula , and bring in x0, y0, x1, y1 to obtain the offset and slope.
- The raw data can be converted into the actual voltage using the following formula:
- Single-ended mode calibration with external reference source
- Select external reference source by configuring the CFG.REF_SEL register, and select single-ended mode by configuring the CFG.MODE register to initialize ADC.
- Use a noise-free power supply to connect to the N terminal by configuring the CFG.CH_N register to start ADC sampling.
- Use a noise-free power supply to connect the ADC external input pin, and record the external input as z at this time (note that the external input is only connected from MSIO_0–MSIO_3).
- Sample 1024 pieces of data and remove the maximum and minimum values to obtain the average of 1022 numbers.
- At this time, the average value is recorded as x0, and the input voltage is recorded as y0.
- Collect another voltage value using the above method, record the average code value as x1, and record the input voltage value as y1.
- Use the formula , and bring in x0, y0, x1, y1 to obtain the offset and slope.
- The raw_data can be converted into the actual voltage using the following formula:
where vref represents the voltage value of the external input as this time.
- Differential-ended mode calibration with external reference source
- Select external reference source by configuring the CFG.REF_SEL register, and select differential-ended mode by configuring the CFG.MODE register to initialize ADC.
- Use two noise-free power supplies to connect to the P terminal and N terminal by configuring the CFG.CH_P register and the CFG.CH_N register to start ADC sampling.
- Use a noise-free power supply to connect the ADC external input pin, and record the external input as z at this time (note that the external input is only connected from MSIO_0–MSIO_3).
- Sample 1024 pieces of data and remove the maximum and minimum values to obtain the average of 1022 numbers.
- At this time, the average value is recorded as x0, and the value of the P terminal voltage minus the N terminal voltage is recorded as y0.
- Collect another voltage value using the above method, record the average code value as x1, and record the input voltage difference as y1.
- Use the formula , and bring in x0, y0, x1, y1 to obtain the offset and slope.
- The raw data can be converted into the actual voltage using the following formula:
where vref represents the voltage value of the external input as this time.
- Temperature sensor calibration
- Select internal reference source by configuring the CFG.REF_SEL register, and select internal 0.8 V reference source by configuring the CFG.BAIS_RES_CTRL register.
- Select single-ended mode by configuring the CFG.MODE register, and select temperature as N-terminal input by configuring the CFG.CH_N register to initialize ADC.
- Put the chip into a constant temperature environment.
- Sample 1024 pieces of data and remove the maximum and minimum values to obtain the average of 1022 numbers.
- At this time, the average value is recorded as x0, and the current temperature is recorded as t0.
- Put the chip into another constant temperature environment.
- Sample 1024 pieces of data and remove the maximum and minimum values to obtain the average of 1022 numbers.
- At this time, the average value is recorded as x1, and the current temperature is recorded as t1.
- Use the formula , and bring in x0, t0, x1, t1 to obtain the offset and slope.
- The raw data can be converted into the actual temperature using the following formula:
- Battery voltage calibration
- Select internal reference source by configuring the CFG.REF_SEL register, and select internal 0.8 V reference source by configuring the CFG.BAIS_RES_CTRL register.
- Select single-ended mode by configuring the CFG.MODE register, and select battery as N-terminal input by configuring the CFG.CH_N register to initialize ADC.
- Use a regulated power supply to supply power to the chip. Note that the power supply voltage of the chip that the ADC can work normally is 2.2 V–3.8 V.
- Sample 1024 pieces of data and remove the maximum and minimum values to obtain the average of 1022 numbers.
- At this time, the average value is recorded as x0, and the current battery voltage is recorded as y0.
- Reselect another voltage value to power the chip.
- Sample 1024 pieces of data and remove the maximum and minimum values to obtain the average of 1022 numbers.
- At this time, the average value is recorded as x1, and the current battery voltage is recorded as y1.
- Use the formula , and bring in x0, y0, x1, y1 to obtain the offset and slope.
- The raw data can be converted into the actual battery voltage using the following formula:
Registers
CFG
- Name: Sense ADC Configuration Register
- Description: This register is used to configure reference, channels, and input mode of ADC.
- Base Address: 0x4000A800
- Offset: 0x00
- Reset Value: 0x0710070A
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31 |
RST |
RW |
0x0 |
Reset SADC. Value:
|
30 |
EN |
RW |
0x0 |
Enable SADC. Value:
|
29:27 |
REF_SEL |
RW |
0x0 |
Reference voltage select Value:
Note: Because the maximum input for any MSIO is supposed to be VBATT, there is no benefit from using an external input higher than VBATT/2. |
26:24 |
REF_HP_MODE |
RW |
0x7 |
Used to define the current in the reference circuit:
|
23:20 |
CH_P |
RW |
0x1 |
Used to define input for channel P: Value:
|
19:16 |
CH_N |
RW |
0x0 |
Used to define input for channel N: Value:
|
15 |
EN_TMP |
RW |
0x0 |
Enable temperature sensor. Value:
|
14 |
EN_VBAT |
RW |
0x0 |
Enable battery sensor. Value:
|
13 |
MODE |
RW |
0x0 |
Used to define operation to either single ended or differential mode. Value:
|
12 |
EN_CAL |
RW |
0x0 |
Used to swap inputs of comparator for offset calibration. Value:
|
11 |
RSVD |
R |
Reserved bit |
|
10:8 |
CODE_IN |
RW |
0x7 |
Used to define dynamic range of ADC. Default: 0x7; for higher input signal frequencies close to Nyquist rate, use 0x1. |
7:4 |
RSVD |
R |
Reserved bits |
|
3:0 |
BIAS_RES_CTRL |
RW |
0xA |
Buffered internal reference Value:
Note: For any specific reference value (Vref), the maximum ADC input is supposed to be 2 x Vref. |
FIFO_RD
- Name: Sense ADC FIFO Output Register
- Description: Reading this register will pop an entry from the sense ADC FIFO.
- Base Address: 0x4000E000
- Offset: 0x00
- Reset Value: 0x00000000
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31:0 |
DATA |
R |
0x0 |
When the register is read, data in the FIFO buffer is accessed. |
FIFO_CTRL
- Name: Sense ADC FIFO Control Register
- Description: This register is used to enable DMA request and set the threshold at which the DMA request is made to the hardware handshake mechanism.
- Base Address: 0x4000E000
- Offset: 0x004
- Reset Value: 0x00010000
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31:17 |
RSVD |
R |
Reserved bits |
|
16 |
DMA_EN |
RW |
0x1 |
|
15:6 |
RSVD |
R |
Reserved bits |
|
5:0 |
THD |
RW |
0x0 |
This is used to set the threshold at which the DMA request is made to the hardware handshake mechanism. |
FIFO_STAT
- Name: Sense ADC Status Register
- Description: This register contains the number of valid data entries in the ADC FIFO memory.
- Base Address: 0x4000E000
- Offset: 0x008
- Reset Value: 0x00000000
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31:17 |
RSVD |
R |
Reserved bits |
|
16 |
FLUSH |
W |
Write 1 to flush FIFO DATA. |
|
15:9 |
RSVD |
Reserved bits |
||
8 |
VAL |
R |
0x0 |
Identify whether FIFO is empty. Value:
|
7 |
RSVD |
R |
Reserved bit |
|
6:0 |
COUNT |
R |
0x0 |
Sense ADC FIFO Count, number of 32-bit words in the FIFO. Maximum value is 0x40 or decimal 64. |
CLK
- Name: Sense ADC Clock Register
- Description: This register selects ADC clock.
- Base Address: 0x4000E000
- Offset: 0x00C
- Reset Value: 0x00000000
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31:19 |
RSVD |
R |
Reserved bits |
|
18:16 |
CLK_SEL_RD |
R |
Actual clock select value |
|
15:3 |
RSVD |
R |
Reserved bits |
|
2:0 |
CLK_SEL |
RW |
0x0 |
SADC clock select Value (Hz):
|
ADC_GET_TKN_SW
- Name: Sense ADC Get Software Token Register
- Description: Read this register to try to get token for software and return the result of the trial.
- Base Address: 0x4000E000
- Offset: 0x018
- Reset Value: 0x00000000
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31:9 |
RSVD |
R |
Reserved bits |
|
8 |
snsadc_tkn_owner_sw |
R |
0x0 |
|
7:1 |
RSVD |
R |
Reserved bits |
|
0 |
snsadc_tkn_locked_sw |
R |
0x0 |
|
ADC_RET_TKN_SW
- Name: Sense ADC Release Software Token Register
- Description: Write any value to this register to release the software token.
- Base Address: 0x4000E000
- Offset: 0x020
- Reset Value: 0x00000000
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31:1 |
RSVD |
R |
Reserved bits |
|
0 |
snsadc_ret_tkn_sw |
W |
0x0 |
Write any value to this bit to release the SW token. |
ADC_GET_TKN_STAT
- Name: Sense ADC Token Status Register
- Description: This register indicates the token status and the token owner.
- Base Address: 0x4000E000
- Offset: 0x024
- Reset Value: 0x00000000
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31:9 |
RSVD |
R |
Reserved bits |
|
8 |
snsadc_tkn_owner |
R |
0x0 |
|
7:1 |
RSVD |
R |
Reserved bits |
|
0 |
snsadc_tkn_locked |
R |
0x0 |
|
Reading this register would not issue any action of getting a token.
Electrical Specifications
Parameter | Symbol | Min. | Typ. | Max. | Unit |
---|---|---|---|---|---|
Physical number of bits |
PNOB |
13 |
bit |
||
Sampling frequency |
Freq |
4 K | 16 M |
Hz | |
Integrated nonlinearity |
INL |
-8 |
8 |
LSB |
|
Differential nonlinearity |
DNL |
-8 |
8 |
LSB |
|
Signal-to-noise and distortion ratio |
SNDR |
60 |
dB |
||
Total harmonic distortion |
THD |
65 |
dB |
||
Effective number of bits |
ENOB |
9.5 |
bit |
||
Differential offset voltage, 13-bit resolution |
Vos |
-4 |
4 |
LSB |
|
Gain error |
Eg |
-1 |
1 |
% |
|
Sampling capacitor |
Cs |
2 |
pF |
||
Sampling rate |
F_S |
0.27 | 1067 |
ksps |
|
Input resistance |
Rin |
> 1 M |
ohm |
||
Current consumption during ADC conversion @100 Ksps |
I_ADC |
< 20 |
μA |
||
Spurious free dynamic range |
SFDR |
68 |
dB |