USB 2.0
Introduction
GR5526 SoC provides a universal serial bus (USB) device controller that is compliant with USB 2.0 Full-Speed specification. The USB device controller supports six endpoints and four data transfer modes: control transfer, bulk transfer, interrupt transfer, and isochronous transfer.
Main Features
-
Complaint with USB 2.0 Full-Speed specification
-
Controllable pull-up/pull-down resistor at D+/D-
-
Integrated USB PHY on GR5526 SoCs
-
Support for six endpoints:
- EP0 as a control endpoint that integrates IN and OUT
- EP1 as an OUT endpoint supporting both interrupt and bulk transfers
- EP2 and EP3 as IN endpoints supporting both interrupt and bulk transfers
- EP4 as an IN endpoint supporting isochronous transfer
- EP5 as an OUT endpoint supporting isochronous transfer
-
Diverse FIFO sizes:
- EP0: 2 x 64 bytes FIFOs
- EP1, EP2, and EP3: 64 bytes FIFO for each
- EP4 and EP5: 1023 bytes FIFO for each
-
DMA (available for EP3, EP4, and EP5 only)
The USB system of GR5526 comprises four modules: a USB device controller (the light blue module in the 图 58), a clock module (clock data recovery submodule and OSC clock generation source), an AON power module (5 V VBUS to 3.3 V LDO), and a USB transceiver module. The figure below shows the block diagram of a USB system.
The USB device controller module contains the following submodules:
- Digital PHY: receives differential signals from the USB transceiver (XCVR). The submodule generates parallel data and converts the data into differential data in NRZI code that will be then transmitted to the USB XCVR.
- UTMI I/F: converts parallel signals into standard USB 2.0 Transceiver Macrocell Interface (UTMI) signals.
- Protocol processing submodule: parses 8-bit parallel data signals received from the UTMI I/F and disassembles the data into different packet fields. The data is then transmitted to the UTMI I/F.
- Endpoint control submodule: controls write/read permissions of endpoints.
- Register submodule: receives control commands from MCU and returns the status and interrupt information of the USB device controller module.
- AON power submodule: detects connection/disconnection of a USB device to/from the host; converts 5 V VBUS supply from the host into 3.3 V supply for the USB XCVR.
Functional Description
Endpoint Configurations
| EP# | Direction | Type | FIFO Size | Functionality | Access | DMA |
|---|---|---|---|---|---|---|
0 |
IN/OUT |
Control |
2 x 64 bytes |
Enumeration/Config |
APB |
Not supported |
1 |
OUT |
Bulk/Interrupt |
64 bytes |
Data from host |
APB |
Not supported |
2 |
IN |
Bulk/Interrupt |
64 bytes |
Data to host |
APB |
Not supported |
3 |
IN |
Bulk/Interrupt |
64 bytes |
Data to host |
AHB/APB |
Supported |
4 |
IN |
Isochronous |
1023 bytes |
Data to host |
AHB/APB |
Supported |
5 |
OUT |
Isochronous |
1023 bytes |
Data from host |
AHB/APB |
Supported |
The data transfer modes of EP1, EP2, and EP3 can be configured to either interrupt or bulk by the MCU through registers before USB reset. Default mode: bulk transfer.
EP0 serves as a standard control endpoint for USB enumeration. EP0 receives device requests from the host and returns descriptors; alternatively, EP0 can obtain configurations of diverse-type data sent out by the host.
EP1 receives data sent out from the host in bulk or interrupt mode. The data can be transferred in a packet of up to 64 bytes, and the data content is parsed by the MCU. After enabling EP1 interrupt transfer, the USB device controller parses data sent out from the host and informs the MCU of the packet size of the received data. The MCU reads related FIFO address to obtain the data.
EP2 sends out information to software on the host side and responds to IN requests that data should be sent to the host in bulk or interrupt mode. The data packet size is up to 64 bytes. The MCU writes to-be-transferred data to a corresponding FIFO address and informs the USB device controller to send out the data after packaging it into a packet. The packet format is defined by software.
In general, EP3 supports bulk transfer of large amounts of data. The EP3 accesses the system RAM in DMA mode as an AHB master. It transmits a large amount of data to the USB host. Alternatively, EP3 supports data write by the MCU(4 bytes align) through Advanced Peripheral Bus (APB) and transmits data to the USB host.
EP4 sends isochronous data to the host and supports a FIFO of 1023 bytes. It can be used to transmit audio data and respond to isochronous IN data requests from the host. Similar to EP3, EP4 supports data write by the MCU at the FIFO entry address through APB and transmits data to the USB host. In addition, EP4 accesses the system RAM in DMA mode as an AHB master.
EP5 receives isochronous data from the host and supports a FIFO of 1023 bytes. It can be used to transmit audio data and respond to isochronous OUT data requests from the host. EP5 enables the MCU to read data at the FIFO entry address through APB. In addition, EP5 accesses the system RAM in DMA mode as an AHB master.
USB Enumeration Methods
GR5526 supports USB enumeration by either hardware or software:
-
By hardware: The built-in finite-state machine (FSM) automatically completes the USB enumeration, not requiring MCU or DMA.
-
By software: The MCU parses and responds to all device requests while EP0 serves as a passthrough channel.
Automatic Hardware-enabled Enumeration
In hardware-enabled enumeration, the built-in FSM controls the enumeration procedures, and EP0 automatically parses and responds to standard device requests sent by the host. The hardware-enabled enumeration features highest enumeration efficiency, fast response, and no timeout. In addition, it requires no support from the MCU and exerts the least impact on system. However, this enumeration approach is less flexible to use compared with software-enabled enumeration (supporting enumeration of some USB devices only).
Descriptors required in hardware-enumeration such as vendor IDs (VID) and product IDs (PID) of USB devices are stored in GR5526 Flash. The hardware enumeration module provides a built-in 256-byte RAM to store enumeration data. Power on the GR5526 SoC, and the MCU writes the descriptors to the RAM through APB in Flash. During enumeration, the FSM reads corresponding descriptors in the RAM and then responds to device requests sent from the host.
Software-enabled Enumeration
In software-enabled enumeration, EP0 serves as a bidirectional data transfer channel, and the USB device controller module does not parse payloads. This makes the software-enabled enumeration flexible to use (supporting enumeration of all USB devices) and allows users to modify MCU firmware files to ensure optimal interoperability.
Software-enabled enumeration steps:
- EP0 sends out an interrupt signal to the MCU after receiving a complete data packet (when an end of packet or EOP signal is detected and CRC validation).
- The MCU processes the interrupt signal and then reads and parses data bytes one after another from the EP0 OUT FIFO (the first byte of a packet indicates the packet size).
- The MCU successively writes the corresponding data including descriptors that are read from Flash into the IN FIFO of EP0 according to the request type.
- When data write completes, set the EP0_1_CTRL register to EP0_DATA_READY by software to inform the USB device controller that the complete data packet has been written to the IN FIFO of EP0.
- EP0 sends the data in the IN FIFO to the USB host in a packet.
Bulk and Interrupt Transfer
After EP1 is enabled, it receives the OUT packet sent by the host based on the configured data transfer type (bulk or interrupt), and parses the payload size in the packet as well as contents saved in its FIFO. EP1 then generates the EP1_OUT_READY interrupt to notify the MCU to read payload of the same size from the FIFO.
When the MCU needs to send messages (including data in response to command(s) to EP1, and the status agreed between the MCU software and the host, such as an interrupt status) to the host, the action should be first permitted by EP2. EP1, EP2, and EP3 are in bulk transfer mode by default. If a specific latency is required, users can configure EP2 to interrupt mode via the MCU prior to data transfer.
During EP2 data transfer:
- The MCU checks the status register EP2_DATA_READY via APB.
- If the space in EP2 FIFO is sufficient, the MCU writes the values read from the register in sequence to the EP2 FIFO in the agreed format. Otherwise, wait until the space becomes sufficient.
- When data write completes, the MCU writes to the EP2_DATA_READY register via APB, to inform USB device controller of data write completion and data ready for transmission, to avoid incomplete data transmission caused by data transfer before data write to FIFO completes.
- When the USB module receives EP2 IN token from the host, it packs and sends the data from the FIFO to the host.
In addition to the functions of EP2, EP3 supports DMA, which enables bulk data transfer from the MCU to the host: Set the allocation address on RAM for DMA transfer and the size of data to be transferred, and enable the DMA function. By default, the USB module allocates data to the EP3 FIFO before data transfer.
- The MCU configures USB registers via APB. Set the condition to trigger EP3 interrupt is when the available space in EP3 FIFO equal to or above 64 bytes.
- The MCU checks whether there are sufficient data for USB data transfer based on DMA interrupt. If no, wait until the data blocks become sufficient; if yes, ask USB host via EP2 to fetch data and then proceed to the next step.
- The MCU configures the AHB master interface module of EP3 [the configuration covers SRAM offset address, total size of data to be transferred, and data size (burst size) in one read operation by AHB].
- AHB master transfers data from the designated address in SRAM to FIFO in the size of one read operation as configured.
- After receiving IN Token from the host, EP3 packs and sends data to the host; if the data transfer (one frame) has not completed, AHB master will continue to transfer data from SRAM until the data transfer completes.
The host software parses messages; USB host only passes through data, and places no limit to the payload format and content.
Isochronous Transfer
EP4 and EP5 only support isochronous data transfer, and each uses its FIFO (1023 bytes) for buffer.
During EP4 data transfer:
- When EP4 sends isochronous data to the host via FIFO:
- Enable TX interrupt of EP4 FIFO and the empty packet function of EP4 (to return a packet with null data before data is ready), and disable the pending state of EP4.
- Query whether EP4 FIFO is sending data; clear data in FIFO if data TX completes.
- Write data to EP4 in every 4 bytes. If the last data segment written to EP4 does not reach 4 bytes, re-configure the size for the last data transfer of EP4 FIFO based on the actual data size (1 byte, 2 bytes, or 3 bytes).
- Set the data transfer status of EP4 FIFO to complete.
- When EP4 sends isochronous data to the host via DMA:
- Enable DMA TX interrupt and the empty packet function of EP4 (to return a packet with null data before data is ready), and disable the pending state of EP4.
- Query whether EP4 is sending data via DMA; clear data in FIFO if DMA data TX completes.
- Set DMA data TX size of EP4 and the RAM entry address to receive data via DMA.
- Enable DMA data TX of EP4 as AHB master.
During EP5 data transfer:
- When EP4 receives isochronous data from the host via FIFO:
- Enable RX interrupt of EP5, and disable the pending state of EP5.
- After receiving the OUT data from the host, EP5 parses the received payload and writes the parsed data to FIFO; it then generates an interrupt EP5_OUT_READY to inform the MCU of the received data size.
- The MCU reads data in accordance with the received data size from the entry address of the EP5 FIFO.
- When EP5 receives isochronous data from the host via DMA:
- Configure the RAM entry address for data transferred via DMA, and the data size to generate interrupt to indicate EP5 DMA RX completes.
- Enable DMA RX interrupt and DMA RX timeout interrupt of EP5, and set the timeout period: If the size of received data does not equal the size to generate an interrupt, an interrupt will be generated after the system times out. Disable the pending state of EP5.
- After receiving the OUT data from the host, EP5 parses the received payload and writes the parsed data to FIFO. Data will be transferred to the RAM address as configured via DMA; data transfer ends when the transferred size reaches the pre-set size, and an interrupt will be generated to inform the MCU of DMA data RX completion.
- If the transferred data size does not reach or exceed the size to generate an interrupt, an interrupt will be generated after the system times out, to inform the MCU of data transfer completion.
Registers
CTRL
Name: USB Control Register
Description: This register controls USB base state.
Base Address: 0x0400A900
Offset: 0x0
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:18 |
RSVD |
R |
Reserved bits |
|
17 |
EP5_OUT_DATA_READY |
RW |
0x0 |
OUT data in EP5 is ready. The MCU will clear this bit after reading the data. |
16 |
EP0_FIFO_SWITCH_EN |
RW |
0x0 |
This bit is used when MCU_ENUM = 0. When hardware enumeration is finished, disable enumeration by hardware. |
15 |
EP1_OUT_DATA_READY |
RW |
0x0 |
OUT data in EP1 is ready. The MCU will clear this bit after reading the data. The USB will issue NAK before the data is read out. |
14:8 |
FUNC_ADDR |
RW |
0x0 |
USB function address. If taking enumeration, the MCU fills in the address; otherwise this field is automatically set by the USB device controller. |
7 |
CMD_ERR |
W |
0x0 |
Error occurs when the MCU interprets the USB device request. 1: Command or OUT data is wrong. 0: No error. |
6 |
CMD_OK |
W |
0x0 |
The MCU interprets the request sent by the host to the USB device.
|
5 |
CFG_STATUS |
RW |
0x0 |
USB is in configured status: If taking enumeration, the MCU fills in the bit; otherwise this field is automatically set by the USB device controller. |
4 |
ADDR_STATUS |
RW |
0x0 |
USB is in configuring address status. If taking enumeration, the MCU fills in the bit; otherwise this field is automatically set by the USB device controller. |
3 |
DEV_REMOTE_WAKEUP |
RW |
0x0 |
REMOTE_WAKEUP feature. If taking enumeration, the MCU sets this bit for USB device; otherwise this bit is automatically set by the USB device controller. |
2 |
MCU_WAKEUP |
W |
0x0 |
The MCU wakes up USB host remotely. When the MCU writes 1 to this bit, and "REMOTE_WAKEUP" feature is set by the host, the USB will wake up the host. This bit will be cleared after USB wakeup. |
1 |
EP0_OUT_DATA_READY |
RW |
0x0 |
OUT data in EP0 is ready. The MCU will clear this bit after reading the data. USB will issue NAK before the data is read out. |
0 |
MCU_ENUM |
RW |
0x0 |
The type of the MCU taking the enumeration process: 0: Hardware-enabled enumeration 1: Software-enabled enumeration (by MCU) |
EP0_1_CTRL
Name: USB EP0 and EP1 Control Register
Description: This register controls USB EP0 and EP1.
Base Address: 0x0400A900
Offset: 0x04
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
Reserved bits |
|
2 |
EP1_OFIFO_CLR |
W |
0x0 |
Write 1 to this bit to clear EP1 OUT FIFO. |
1 |
EP0_IFIFO_CLR |
W |
0x0 |
Write 1 to this bit to clear EP0 IN FIFO. |
0 |
EP0_DATA_READY |
RW |
0x0 |
The bit is set by MCU when MCU has sent all data to EP0 IN FIFO. The bit is set by USB device controller when IN FIFO has max-packet-size data to transfer. After USB device controller sends all EP0 data, it will clear this bit. MCU shall poll this bit before send data to EP0 FIFO, and cannot write data until this bit is cleared. |
EP2_CTRL
Name: USB EP2 Control Register
Description: This register controls USB EP2.
Base Address: 0x0400A900
Offset: 0x08
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:2 |
RSVD |
R |
Reserved bits |
|
1 |
EP2_IFIFO_CLR |
W |
0x0 |
Write 1 to this bit to clear EP2 IN FIFO. |
0 |
EP2_DATA_READY |
RW |
0x0 |
The bit is set by MCU when MCU has sent all data to EP2 IN FIFO. The bit is set by USB device controller when IN FIFO has max-packet-size data to transfer. After USB device controller sends all EP2 data, it will clear this bit. MCU shall poll this bit before sending data to EP2 FIFO, and cannot write data until this bit is cleared. |
EP3_CTRL
Name: USB EP3 Control Register
Description: This register controls USB EP3.
Base Address: 0x0400A900
Offset: 0x0C
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:2 |
RSVD |
R |
Reserved bits |
|
1 |
EP3_IFIFO_CLR |
W |
0x0 |
Write 1 to this bit to clear EP3 IN FIFO. |
0 |
EP3_DATA_READY |
RW |
0x0 |
The bit is set by MCU when MCU has sent all data to EP3 IN FIFO. The bit is set by USB controller when IN FIFO has max-packet-size data to transfer. After USB device controller sends all EP3 data, it will clear this bit. MCU shall poll this bit before send data to EP3 FIFO, and cannot write data until this bit is cleared. |
EP_ATTR
Name: USB Set Endpoint Attribute Register
Description: This register sets USB EP1, EP2 and EP3 attribute.
Base Address: 0x0400A900
Offset: 0x10
Reset Value: 0x00000202
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:11 |
RSVD |
R |
Reserved bits |
|
10 |
EP3_HALT_MCU |
RW |
0x0 |
Set this bit to halt EP3. |
8:9 |
EP3_ATTR |
RW |
0x2 |
EP3 attribute setting: 00: Interrupt 01: Isochronous 10: Bulk 11: Undefined MCU must keep this data consistent with the content of descriptor. |
7 |
RSVD |
R |
Reserved bits |
|
6 |
EP2_HALT_MCU |
RW |
0x0 |
Set this bit to halt EP2. |
4:5 |
EP2_ATTR |
RW |
0x0 |
EP2 attribute setting: 00: Interrupt 01: Isochronous 10: Bulk 11: Undefined MCU must keep this data consistent with the content of descriptor. |
3 |
RSVD |
R |
Reserved bits |
|
2 |
EP1_HALT_MCU |
RW |
0x0 |
Set this bit to halt EP1 |
0:1 |
EP1_ATTR |
RW |
0x2 |
EP1 attribute setting: 00: Interrupt 01: Isochronous 10: Bulk 11: Undefined MCU must keep this data consistent with the content of descriptor. |
INT_STAT
Name: USB Interrupt Status Register
Description: This register returns the interrupt status of USB.
Base Address: 0x0400A900
Offset: 0x14
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:26 |
RSVD |
R |
Reserved bits |
|
25 |
EP5_TIMER_OUT_ERR |
R |
0x0 |
AHB master EP5 transmission timeout error. |
24 |
EP5_AHB_XFER_DONE |
R |
0x0 |
AHB master EP5 transfer done. |
23 |
EP4_DAT_SENT |
R |
0x0 |
The data in the EP4 IN FIFO has been sent to the host. |
22 |
EP4_AHB_XFER_DONE |
R |
0x0 |
AHB master EP4 transfer done. |
21 |
EP5_OUT_READY |
R |
0x0 |
The data in the EP5 from the USB host is ready. |
20 |
INTO_CONFIG |
R |
0x0 |
The hardware enters the enumeration status, and is valid when MCU_ENUM = 0. |
19 |
EP3_DAT_SENT |
R |
0x0 |
The data in the EP3 IN FIFO has been sent to the host. |
18 |
EP2_DAT_SENT |
R |
0x0 |
The data in the EP2 IN FIFO has been sent to the host. |
17 |
EP0_DAT_SENT |
R |
0x0 |
The data in the EP0 IN FIFO has been sent to the host. |
16 |
SOF |
R |
0x0 |
SOF interrupt. |
15 |
BYTE_ERR |
R |
0x0 |
USB byte error. |
14 |
BIT_STUFF_ERR |
R |
0x0 |
USB bit stuff error. |
13 |
SYNC_ERR |
R |
0x0 |
USB SYNC error. |
12 |
AHB_EP3_XFER_DONE |
R |
0x0 |
AHB master EP3transfer done. |
11 |
NSE_ERR |
R |
0x0 |
No such endpoint error. |
10 |
AHB_EP3_XFER_ERR |
R |
0x0 |
AHB master EP3 receives error response. |
9 |
HOST_RESET |
R |
0x0 |
USB host reset. |
8 |
PID_CRC_ERR |
R |
0x0 |
PID CRC error. |
7 |
PID_CKS_ERR |
R |
0x0 |
PID checksum error. |
6 |
SEQ_ERR |
R |
0x0 |
DATA0/DATA1 PID sequence error. |
5 |
TO_ERR |
R |
0x0 |
RX/TX timeout error. |
4 |
UPID_ERR |
R |
0x0 |
Receive unsupported PID error. |
3 |
CRC16_ERR |
R |
0x0 |
Receive CRC error data. |
2 |
EP1_OUT_READY |
R |
0x0 |
The data in the EP1 from the USB host is ready. |
1 |
EP0_OUT_READY |
R |
0x0 |
The setup data in the EP0 from the USB host is ready. |
0 |
USB_SUSPEND |
R |
0x0 |
MCU takes the enumeration process. USB device controller will turn to the suspended status. |
INT_EN
Name: USB Interrupt Enable Register
Description: This register enables USB interrupts.
Base Address: 0x0400A900
Offset: 0x18
Reset Value: 0x003EFDFF
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:26 |
RSVD |
R |
Reserved bits |
|
25 |
EP5_TIMER_OUT_ERR_EN |
RW |
0x01 |
Enable EP5 transfer timeout interrupt. |
24 |
EP5_AHB_XFER_DONE_EN |
RW |
0x01 |
Enable AHB master EP5 transfer done interrupt. |
23 |
EP4_DAT_SENT_EN |
RW |
0x01 |
Enable the interrupt source: Data in the EP4 IN FIFO has been sent to the host. |
22 |
EP4_AHB_XFER_DONE_EN |
RW |
0x01 |
Enable AHB master EP4 transfer done interrupt. |
21 |
EP5_OUT_READY_EN |
RW |
0x01 |
Enable the interrupt source: Data in endpoint5 from USB host is ready. |
20 |
INTO_CONFIG_EN |
RW |
0x0 |
Enable the interrupt that the hardware completes enumeration process and enters the configured status, which is valid when EP0_FIFO_SWITCH_EN = 1. |
19 |
EP3_DAT_SENT_EN |
RW |
0x01 |
Enable the interrupt that EP3 IN FIFO data has been sent to the host. |
18 |
EP2_DAT_SENT_EN |
RW |
0x0 |
Enable the interrupt that EP2 IN FIFO data has been sent to the host. |
17 |
EP0_DAT_SENT_EN |
RW |
0x01 |
Enable the interrupt that EP0 IN FIFO data has been sent to host. |
16 |
SOF_EN |
RW |
0x01 |
Enable the SOF interrupt. |
15 |
BYTE_ERR_EN |
RW |
0x01 |
Enable the USB byte error interrupt. |
14 |
BIT_STUFF_ERR_EN |
RW |
0x01 |
Enable the USB bit stuff error interrupt. |
13 |
SYNC_ERR_EN |
RW |
0x0 |
Enable the USB SYNC error interrupt. |
12 |
AHB_EP3_XFER_DONE_EN |
RW |
0x01 |
Enable the AHB master EP3 transfer done interrupt. |
11 |
NSE_ERR_EN |
RW |
0x01 |
Enable the no such endpoint error interrupt. |
10 |
AHB_EP3_XFER_ERR_EN |
RW |
0x01 |
Enable the interrupt source: AHB master EP3 receives ERROR response. |
9 |
HOST_RESET_EN |
RW |
0x01 |
Enable USB host reset interrupt. |
8 |
PID_CRC_ERR_EN |
RW |
0x01 |
Enable PID CRC error interrupt. |
7 |
PID_CKS_ERR_EN |
RW |
0x01 |
Enable PID checksum error interrupt. |
6 |
SEQ_ERR_EN |
RW |
0x01 |
Enable DATA0/DATA1 PID sequence error interrupt. |
5 |
TO_ERR_EN |
RW |
0x01 |
Enable RX/TX timeout error interrupt. |
4 |
UPID_ERR_EN |
RW |
0x01 |
Enable receiving unsupported PID interrupt. |
3 |
CRC16_ERR_EN |
RW |
0x01 |
Enable receiving CRC error data interrupt. |
2 |
EP1_OUT_READY_EN |
RW |
0x01 |
Enable the interrupt that the data in EP1 from USB host is ready. |
1 |
EP0_OUT_READY_EN |
RW |
0x01 |
Enable the interrupt that setup data in EP0 from USB host is ready. |
0 |
USB_SUSPEND_EN |
RW |
0x01 |
Enable the interrupt that MCU takes the enumeration process of USB controller turning to suspended status. |
INT_CLR
Name: USB Interrupt Clear Register
Description: This register clears USB interrupts.
Base Address: 0x0400A900
Offset: 0x1C
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:26 |
RSVD |
R |
Reserved bits |
|
25 |
EP5_TIMER_OUT_ERR_CLR |
W |
0x0 |
Clear EP5 transfer timeout interrupt. |
24 |
EP5_AHB_XFER_DONE_CLR |
W |
0x0 |
Clear AHB master EP5 transfer done interrupt. |
23 |
EP4_DAT_SENT_CLR |
W |
0x0 |
Clear the interrupt source: Data in the EP4 IN FIFO has been sent to the host. |
22 |
EP4_AHB_XFER_DONE_CLR |
W |
0x0 |
Clear AHB master EP4 transfer done interrupt. |
21 |
EP5_OUT_READY_CLR |
W |
0x0 |
Clear the interrupt source: Data in endpoint5 from USB host is ready. |
20 |
INTO_CONFIG_CLR |
W |
0x0 |
Clear the interrupt source: The hardware completes enumeration process and enters the configured status, which is valid when EP0_FIFO_SWITCH_EN = 1. |
19 |
EP3_DAT_SENT_CLR |
W |
0x0 |
Clear the interrupt source: EP3 IN FIFO data has been sent to the host. |
18 |
EP2_DAT_SENT_CLR |
W |
0x0 |
Clear the interrupt source: EP2 IN FIFO data has been sent to the host. |
17 |
EP0_DAT_SENT_CLR |
W |
0x0 |
Clear the interrupt source: EP0 IN FIFO data has been sent to host. |
16 |
SOF_CLR |
W |
0x0 |
Clear the SOF interrupt. |
15 |
BYTE_ERR_CLR |
W |
0x0 |
Clear the USB byte error interrupt. |
14 |
BIT_STUFF_ERR_CLR |
W |
0x0 |
Clear the USB bit stuff error interrupt. |
13 |
SYNC_ERR_CLR |
W |
0x0 |
Clear the USB SYNC error interrupt. |
12 |
AHB_EP3_XFER_DONE_CLR |
W |
0x0 |
Clear the AHB master EP3 transfer done interrupt. |
11 |
NSE_ERR_CLR |
W |
0x0 |
Clear the no such endpoint error interrupt. |
10 |
AHB_EP3_XFER_ERR_CLR |
W |
0x0 |
Clear the interrupt source: AHB master EP3 receives error response. |
9 |
HOST_RESET_CLR |
W |
0x0 |
Clear USB host reset interrupt. |
8 |
PID_CRC_ERR_CLR |
W |
0x0 |
Clear PID CRC error interrupt. |
7 |
PID_CKS_ERR_CLR |
W |
0x0 |
Clear PID checksum error interrupt. |
6 |
SEQ_ERR_CLR |
W |
0x0 |
Clear DATA0/DATA1 PID sequence error interrupt. |
5 |
TO_ERR_CLR |
W |
0x0 |
Clear RX/TX timeout error interrupt. |
4 |
UPID_ERR_CLR |
W |
0x0 |
Clear receiving unsupported PID interrupt. |
3 |
CRC16_ERR_CLR |
W |
0x0 |
Clear receiving CRC error data interrupt. |
2 |
EP1_OUT_READ_CLR Y |
W |
0x0 |
Clear the interrupt source: Data in EP1 from USB host is ready. |
1 |
EP0_OUT_READY_CLR |
W |
0x0 |
Clear the interrupt source: Setup data in EP0 from USB host is ready. |
0 |
USB_SUSPEND_CLR |
W |
0x0 |
Clear the interrupt source: MCU takes the enumeration process of USB device controller turning to suspended status. |
EP3_AHBM_RADDR
Name: AHB Master EP3 Reads Start Address Register
Description: This register enables the AHB master EP3 to read the start address.
Base Address: 0x0400A900
Offset: 0x20
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
EP3_RD_SADDR |
RW |
0x0 |
AHB master EP3 reads start address |
EP3_AHMB_CTRL
Name: AHB Master EP3 Reads Control Register
Description: This register controls AHB master EP3.
Base Address: 0x0400A900
Offset: 0x24
Reset Value: 0x00004000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:8 |
EP3_AHBM_BURST_SIZE |
RW |
0x40 |
AHB master EP3 burst length; default 64 bytes. |
7:1 |
RSVD |
R |
Reserved bits |
|
0 |
EP3_AHBM_EN |
RW |
0x0 |
Enable AHB master EP3. |
CTRL0
Name: USB Control 0 Register
Description: This register controls USB PHY.
Base Address: 0x0400A900
Offset: 0x28
Reset Value: 0x00000048
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:19 |
RSVD |
R |
Reserved bits |
|
18:16 |
PROBE_SEL |
RW |
0x0 |
Probe selection signal:
|
15 |
RXD |
R |
0x0 |
RXD real time status. |
14 |
INPUT_EDIAN_CTRL |
RW |
0x0 |
1: Data is in big endian. 0: Data is in small endian. |
13 |
OUTPUT_ENDIAN_CTRL |
RW |
0x0 |
1: Data is in big endian. 0: Data is in small endian. |
12:10 |
RSVD |
R |
Reserved bits |
|
9 |
XCVR_DM_RPD_EN |
RW |
0x0 |
Set this bit to drive DM to pull down in transceiver test mode. |
8 |
XCVR_DP_RPD_EN |
RW |
0x0 |
Set this bit to drive Data plus (D+) to pull down in transceiver test mode. |
7 |
XCVR_DM_RPUSW_EN |
RW |
0x0 |
Set this bit to drive DM software to pull up in transceiver test mode. |
6 |
XCVR_DP_RPUSW_EN |
RW |
0x01 |
Set this bit to drive DP SW to pull up in transceiver test mode. In function mode, this bit is driven by USB controller and cannot be set. |
5 |
XCVR_DM_RPU_EN |
RW |
0x0 |
Set this bit to drive DM to pull up in transceiver test mode. |
4 |
XCVR_DP_RPU_EN |
RW |
0x0 |
Set this bit to drive DP to pull up in transceiver test mode. In function mode, this bit is driven by USB controller and cannot be set. |
3 |
XCVR_OEB |
RW |
0x01 |
Drive output enable buffer (OEB) in transceiver test mode. |
2 |
DRIVE_DM |
RW |
0x0 |
Drive DM in transceiver test mode. Read this bit to get the DM status. |
1 |
DRIVE_DP |
RW |
0x0 |
Drive DP in transceiver test mode. Read this bit to get the DP status. |
0 |
TEST_MODE |
RW |
0x0 |
0: Function mode 1: USB transceiver test mode |
EP3_XFER_LEN
Name: USB Total EP3 Transfer Length Register
Description: This register sets the total USB EP3 transfer length.
Base Address: 0x0400A900
Offset: 0x2C
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:0 |
EP3_XFER_LEN |
RW |
0x0 |
Total USB EP3 transfer length. MCU should set this field for AHB transfer. |
RX_CNT
Name: USB Received Data Sum Register
Description: This register gets received data sum in the EP0 FIFO and EP1 FIFO.
Base Address: 0x0400A900
Offset: 0x30
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:8 |
EP1_RX_DATA_SUM |
R |
0x0 |
USB receives data sum in the EP1 FIFO. |
7:0 |
EP0_RX_DATA_SUM |
R |
0x0 |
USB receives data sum in the EP0 FIFO. |
CFG_DESC_CTRL
Name: USB Config Descriptor Control Register
Description: This register controls USB config descriptor in hardware-enabled enumeration.
Base Address: 0x0400A900
Offset: 0x34
Reset Value: 0x00004912
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:8 |
CFG_DESC_SIZE |
RW |
0x49 |
Config descriptor size. |
7:0 |
CFG_DESC_START |
RW |
0x12 |
Config descriptor start address. |
STR_DESC0_CTRL
Name: USB Language ID Descriptor Control Register
Description: This register controls USB language ID descriptor in hardware-enabled enumeration.
Base Address: 0x0400A900
Offset: 0x38
Reset Value: 0x00000470
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:8 |
STR_DESC0_SIZE |
RW |
0x4 |
Language ID descriptor size |
7:0 |
STR_DESC0_START |
RW |
0x70 |
Language ID descriptor start address |
STR_DESC1_CTRL
Name: USB String Descriptor Control Register
Description: This register controls USB string descriptor in hardware-enabled enumeration.
Base Address: 0x0400A900
Offset: 0x3C
Reset Value: 0x00001290
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:8 |
STR_DESC1_SIZE |
RW |
0x12 |
String descriptor size |
7:0 |
STR_DESC1_START |
RW |
0x90 |
String descriptor start address |
EP0_FIFO_ADDR
Name: USB EP0 FIFO Address Register
Description: This register reads or sends USB EP0 FIFO data.
Base Address: 0x0400A900
Offset: 0x40
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
USB_EP0_FIFO |
RW |
0x0 |
USB EP0 FIFO address. |
EP1_FIFO_ADDR
Name: USB EP1 FIFO Address Register
Description: This register reads USB EP1 FIFO data.
Base Address: 0x0400A900
Offset: 0x44
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
USB_EP1_FIFO |
R |
0x0 |
USB EP1 FIFO address. |
EP2_FIFO_ADDR
Name: USB EP2 FIFO Address Register
Description: This register sends data to USB EP2 FIFO.
Base Address: 0x0400A900
Offset: 0x48
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
USB_EP2_FIFO |
W |
0x0 |
USB EP2 FIFO address. |
EP3_FIFO_ADDR
Name: USB EP3 FIFO Address Register
Description: This register sends data to USB EP3 FIFO.
Base Address: 0x0400A900
Offset: 0x4C
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
USB_EP3_FIFO |
W |
0x0 |
USB EP3 FIFO address. |
SRAM_ADDR
Name: USB Descriptor SRAM Address Register
Description: This register indicates USB descriptor SRAM address in hardware-enabled enumeration.
Base Address: 0x0400A900
Offset: 0x50
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
USB_DESC_SRAM |
W |
0x0 |
USB descriptor SRAM address |
STR_DESC2_CTRL
Name: USB String2 Descriptor Control Register
Description: This register controls USB string2 descriptor in hardware-enabled enumeration.
Base Address: 0x0400A900
Offset: 0x54
Reset Value: 0x00000A60
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:8 |
STR_DESC2_SIZE |
RW |
0x0A |
When wValue[3:0] = 4'h2, string descriptor size (for string descriptor) should be reserved. |
7:0 |
STR_DESC2_START |
RW |
0x60 |
When wValue[3:0] = 4'h2, descriptor start address (for string descriptor) should be reserved. |
STR_DESC3_CTRL
Name: USB String3 Descriptor Control Register
Description: This register controls USB string3 descriptor in hardware-enabled enumeration.
Base Address: 0x0400A900
Offset: 0x58
Reset Value: 0x00000A70
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:8 |
STR_DESC3_SIZE |
RW |
0x0A |
When wValue[3:0] = 4'h3, string descriptor size (for string descriptor) should be reserved. |
7:0 |
STR_DESC3_START |
RW |
0x70 |
When wValue[3:0] = 4'h3, descriptor start address(for string descriptor) should be reserved. |
EP4_CTRL
Name: USB EP4 Control Register
Description: This register controls USB EP4.
Base Address: 0x0400A900
Offset: 0x60
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
Reserved bits |
|
2 |
EP4_EMPTY_PACKET_EN |
RW |
0x0 |
Enable EP4 empty packet. |
1 |
EP4_IFIFO_CLR |
W |
0x0 |
Write 1 to this bit to clear EP4 IN FIFO. |
0 |
EP4_DATA_READY |
RW |
0x0 |
The bit is set by MCU when MCU has sent all data to EP4 IN FIFO. The bit is set by USB device controller when IN FIFO has max-packet-size data to transfer. After USB sends all the EP4 data, it will clear this bit. MCU shall poll this bit before sending data to EP4 FIFO, and cannot write data until this bit is cleared. |
EP4_AHBM_RADDR
Name: AHB Master EP4 Reads Start Address Register
Description: This register enables the AHB master EP4 to read the start address.
Base Address: 0x0400A900
Offset: 0x64
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
EP4_RD_SADDR |
RW |
0x0 |
AHB master EP4 reads start address. |
EP4_AHBM_CTRL
Name: AHB Master EP4 Reads Control Register
Description: This register controls AHB master EP4.
Base Address: 0x0400A900
Offset: 0x68
Reset Value: 0x0003FF00
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:18 |
RSVD |
R |
Reserved bits |
|
17:8 |
EP4_AHBM_BURST_SIZE |
RW |
0x3FF |
AHB master EP4 burst length is 32 bytes to 1023 bytes; default: 1023 bytes. |
7:1 |
RSVD |
R |
Reserved bits |
|
0 |
EP3_AHBM_EN |
RW |
0x0 |
Enable AHB master EP4. |
EP4_XFER_LEN
Name: USB Total EP4 Transfer Length Register
Description: This register sets total transfer length of USB EP4.
Base Address: 0x0400A900
Offset: 0x6C
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:0 |
EP4_XFER_LEN |
RW |
0x0 |
USB total EP4 transfer length. MCU should set this field for AHB transfer. |
EP4_FIFO_WEN
Name: USB EP4 FIFO Writing Byte Enable Register
Description: This register enables writing byte for USB EP4 FIFO.
Base Address: 0x0400A900
Offset: 0x80
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:4 |
RSVD |
R |
Reserved bits |
|
3:0 |
EP4_FIFO_WEN |
RW |
0x1 |
This register enables writing byte for USB EP4 FIFO |
EP4_FIFO_ADDR
Name: USB EP4 FIFO Address Register
Description: This register sends data to USB EP4 FIFO.
Base Address: 0x0400A900
Offset: 0x84
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
USB_EP4_FIFO |
W |
0x0 |
USB EP4 FIFO address |
EP5_CTRL
Name: USB EP5 Control Register
Description: This register controls USB EP5.
Base Address: 0x0400A900
Offset: 0x70
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:3 |
RSVD |
R |
Reserved bits |
|
2 |
EP5_RX_CNT_NO_OVERWIRTE |
RW |
0x0 |
0: EP5_RX_DATA_SUM can be overwritten. 1: EP5_RX_DATA_SUM cannot be overwritten until it has been read. |
1 |
EP5_IFIFO_CLR |
W |
0x0 |
Write 1 to this bit to clear EP5 OUT FIFO. |
0 |
EP5_AHBM_EN |
RW |
0x0 |
Enable AHB master EP5. |
EP5_AHBM_RADDR
Name: AHB Master EP5 Writing Start Address Register
Description: The register enables the AHB master EP5 to write the start address.
Base Address: 0x0400A900
Offset: 0x74
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
EP5_WR_SADDR |
RW |
0x0 |
AHB master EP5 writing start address. |
EP5_XFER_LEN
Name: USB Total EP5 Transfer Length Register
Description: This register sets total transfer length OF USB EP5.
Base Address: 0x0400A900
Offset: 0x78
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:0 |
EP5_XFER_LEN |
RW |
0x0 |
USB total EP5 transfer length. MCU should set this field for AHB transfer. |
EP5_TIMER
Name: EP5 Isochronous Data Out Timer Register
Description: This register indicates the OUT timer value of isochronous data transfer of EP5.
Base Address: 0x0400A900
Offset: 0x7C
Reset Value: 0x00000001
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:0 |
USB_EP5_TIMER |
RW |
0x1 |
EP5 isochronous out timer value is 1 to 1000 ms. If this field is set to 0, EP5 will never time out. |
EP5_FIFO_ADDR
Name: USB EP5 FIFO Address Register
Description: This register reads USB EP5 FIFO data.
Base Address: 0x0400A900
Offset: 0x88
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
USB_EP5_FIFO |
R |
0x0 |
USB EP5 FIFO address |
EP5_RX_CNT
Name: USB Endpoint5 Received Data Sum Register
Description: This register gets the received data sum in USB Endpoint5.
Base Address: 0x0400A900
Offset: 0x8C
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:0 |
EP5_RX_DATA_SUM |
R |
0x0 |
USB received data sum in the EP5 transfer. |
USB_DEBUG
Name: USB Debug Register
Description: This register is used for USB debugging.
Base Address: 0x0400A900
Offset: 0x90
Reset Value: 0x00000150
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:20 |
RSVD |
R |
Reserved bits |
|
19 |
EP5_OUT_READY_FLAG |
WC |
0x0 |
Ep5 output ready flag; write 1 to clear it |
18 |
EP4_DAT_SENT_FLAG |
WC |
0x0 |
Ep4 data sent flag; write 1 to clear it |
17 |
EP5_WR_ERR |
WC |
0x0 |
Ep5 write err flag; write 1 to clear it |
16 |
EP4_EMTY_PACKET |
WC |
0x0 |
Ep4 empty packet flag; write 1 to clear it |
15:9 |
RSVD |
R |
0x0 |
Reserved bits |
8 |
EP5_FIFO_EMPTY |
R |
0x1 |
Ep5 FIFO empty flag |
7 |
EP4_FIFO_FULL |
R |
0x0 |
Ep4 FIFO full flag |
6 |
EP4_FIFO_EMPTY |
R |
0x1 |
Ep4 FIFO empty flag |
5 |
EP3_FIFO_FULL |
R |
0x0 |
Ep3 FIFO full flag |
4 |
EP3_FIFO_EMPTY |
R |
0x1 |
Ep3 FIFO empty flag |
3:0 |
USB_PROBE |
R |
0x0 |
State output based on probe_sel[2:0] |
USB_TRX_LDO
Name: USB LDO Control Register
Description: This register controls USB LDO.
Base Address: 0x4000A884
Offset: 0x00
Reset Value: 0x00000001
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:11 |
RSVD |
R |
Reserved bits |
|
10:8 |
USB_RG_LDO3V3_VSEL |
RW |
0x0 |
USB LDO trimming is used to adjust LDO3V3 voltage. |
7:5 |
RSVD |
R |
Reserved bits |
|
6:4 |
USB_RG_LDO3V3_BIAS_SEL |
RW |
0 |
USB LDO trimming is used to adjust D+/D- rise and fall time. |
3:1 |
RSVD |
R |
Reserved bits |
|
0 |
USB_RG_LDO3V3_LP_EN |
RW |
0 |
1: Enable USB LDO low power mode. 0: Disable USB LDO low power mode. |
USB_LP_CTRL
Name: USB Low Power Control Register
Description: This register controls USB low power mode.
Base Address: 0x4000E140
Offset: 0x00
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:9 |
RSVD |
R |
Reserved bits |
|
8 |
USB_CLK_FORCE_OFF |
RW |
0x0 |
0: Follow usb_suspend_clk_off. 1: Force usb_clk off. |
7:5 |
RSVD |
R |
Reserved bits |
|
4 |
USB_PMU_LP_EN |
RW |
0 |
0: Disable USB PMU low power mode. 1: Enable USB PMU low power mode. |
3:1 |
RSVD |
R |
Reserved bits |
|
0 |
USB_SUSPEND_CLK_OFF |
RW |
0 |
Turn off USB clock during USB suspend. |
USB_XCVR_CTRL
Name: USB Transceiver Control Register
Description: This register controls USB transceiver.
Base Address: 0x4000E140
Offset: 0x04
Reset Value: 0x0000000F
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:9 |
RSVD |
R |
Reserved bits |
|
10:8 |
USB_RG_XCVR_RTRIMP |
RW |
0 |
USB D+ trimming is used to adjust D+ impedance. |
6:4 |
USB_RG_XCVR_RTRIMN |
RW |
0 |
USB D- trimming is used to adjust D- impedance. |
3 |
USB_RG_XCVR_BIAS_EN |
RW |
1 |
Reserved bits |
2 |
USB_RG_XCVR_SUSPEND |
RW |
1 |
USB suspend control 0: Disable 1: Enable |
1 |
USB_RG_XCVR_SPEED |
RW |
1 |
1: Full speed 0: Slow speed |
0 |
USB_RG_XCVR_SECMP_PD |
RW |
1 |
USB single end comparator power down control 0: Power up 1: Power down |
USB_SW_RST
Name: USB Module All Reset Control Register
Description: This register controls USB reset.
Base Address: 0x4000E140
Offset: 0x0C
Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:1 |
RSVD |
R |
Reserved bits |
|
0 |
USB_SOFTWARE_RESET |
W |
0 |
Write 1 to reset USB. No need to manually write it back to 0. |
Electrical Specifications
| Symbol | Description | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|
IUSB,ACTIVE,VBUS |
Current from VBUS supply, USB active |
2.7 |
mA |
||
IUSB,SUSPEND,VBUS |
Current from VBUS supply, USB suspended |
360 |
µA |
||
IUSB,DISABLED,VBUS |
Current from VBUS supply, USB disabled (low power mode) |
0.8 |
1.1 |
1.3 |
µA |
RUSB,PU,ACTIVE |
Value of pull-up resistance on D+, bus active |
1425 |
2600 |
3090 |
Ω |
RUSB,PU,IDLE |
Value of pull-up resistance on D+, bus idle |
900 |
1500 |
1575 |
Ω |
fUSB,CLK |
Frequency of local clock, USB active |
48 |
MHz |
