PSRAM

The GR5526VGBIP and GR5526RGNIP SoCs have an 8 MB PSRAM. PSRAM uses OSPI for data access. The OSPI address mapping is used to map PSRAM space to 0x30080000 area, which is helpful for users to access this memory space. Pin definitions are shown in 表 21.

表 21 Pin definitions
Symbol	Type	Description
VDD	Power	Core supply 1.8 V
VDDQ	Power	IO supply 1.8 V
VSS	Ground	Core supply ground
VSSQ	Ground	IO supply ground
A/DQ[7:0]	IO	Address/DQ bus[7:0]
DQS/DM	IO	DQ Strobe (DQS) clock during reads, data mask during writes. DM (Data Mask) is active high. DM = 1 means “do not write”.
CE#	Input	Chip select, active low. When CE# = 1, chip is in standby state.
CLK	Input	Clock signal

Specifications

Single supply voltage:
- VDD: 1.62 to 1.98 V
- VDDQ: 1.62 to 1.98 V
Interface: OSPI, two bytes transferred per one clock cycle
Performance: Only 48 MHz clock rate is supported, up to 70 MB/s read/write throughput
Organization: 8 MB with 1024 Bytes page size
Refresh: Self-managed
Operating temperature range:
- Tc: -40°C to +85°C (standard range)
Maximum standby current:
- 300 μA @ 105°C
- 200 μA @ 85°C
- 100 μA @ 25°C
- 30 μA @ 25°C (half sleep mode with data retained)

Features

Low power features
- Partial array self-refresh
- Auto Temperature Compensated Self-Refresh (ATCSR) by built-in temperature sensor
- User-configurable refresh rate
- Ultra Low Power (ULP) in half sleep mode with data retained
Software reset
Output driver LVCMOS with programmable drive strength
Data Mask for writing data
Data Strobe enables high-speed read operation
Register-configurable write and read initial latencies
Write burst length with a maximum of 1024 bytes and a minimum of 2 bytes
Wrap and hybrid burst in 16 B/32 B/64 B/1 KB lengths
Linear burst command
Row boundary crossing (RBX)
- Read operations can be enabled via Mode Register
- RBX write is not supported

Functional Description

PSRAM is byte-addressable. Memory accesses are required to start on both even and odd addresses, but starting memory access at even addresses is more efficient than starting memory access at odd addresses (example, A[0] = 0). Mode Register accesses allow both even and odd addresses.

The modes of read and write operations are in default Hybrid Wrap 32 mode. Other burst lengths of 16 B, 32 B, 64 B or 1 KB in standard or hybrid wrap modes are configurable by using registers, as shown in the table below. The PSRAM also includes command for linear bursting. Bursts can start on any even address. Write burst length has a minimum of 2 bytes. Read has no minimum length.

表 22 Wrap mode configuration
Register MR8[2]	Register MR8[1:0]	Burst Length	Example of Sequence of Bytes During Wrap
Register MR8[2]	Register MR8[1:0]	Burst Length	Starting Address	Byte Sequence
0b’0	0b’00	16 Byte Wrap	4	[4,5,6,…,15,0,1,2,3,…]
0b’0	0b’01	32 Byte Wrap	4	[4,5,6,…,31,0,1,2,3,…]
0b’0	0b’10	64 Byte Wrap	4	[4,5,6,…,63,0,1,2,3,…]
0b’0	0b’11	1K Byte Wrap	4	[4,5,6,…,1023,0,1,2,3,…]
0b’1	0b’00	16 Byte Hybrid Wrap	2	[2,3,4,…,15,0,1],16,17,…,1023, 0,1,…]
0b’1	0b’01	32 Byte Hybrid Wrap	2	[2,3,4,…,31,0,1],32,33,…,1023, 0,1,…]
0b’1	0b’10	64 Byte Hybrid Wrap	2	[2,3,4,…,63,0,1],64,65,…,1023, 0,1,…]
0b’1	0b’11	1k Byte Hybrid Wrap	2	[2,3,4,…,1023,0,1,2,…]

PSRAM supports the following instructions and follows a certain timing.

表 23 Supported instructions
	1st CLK	2nd CLK		3rd CLK
	Rising/Falling edge	Rising edge	Falling edge	Rising edge	Falling edge
Command	Instruction	Address[31:24]	Address[23:16]	Address[15:8]	Address[7:0]
Sync Read	00h	A3	A2	A1	A0
Sync Write	80h	A3	A2	A1	A0
Sync Read (Linear Burst)	20h	A3	A2	A1	A0
Sync Write (Linear Burst)	A0h	A3	A2	A1	A0
Mode Register Read	40h	-	-	-	Mode Register Address
Mode Register Write	C0h	-	-	-	Mode Register Address
Global Reset	FFh	-	-	-	-

The PASR bits restrict refresh operations to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map.

表 24 Self refresh zone configuration
Register MR4[2:0]	Refresh Coverage	Address Space	Size
0b’000	Full array (default)	000000h-7FFFFFh	8 MB
0b’001	Bottom 1/2 array	000000h-3FFFFFh	4 MB
0b’010	Bottom 1/4 array	000000h-1FFFFFh	2 MB
0b’011	Bottom 1/8 array	000000h-0FFFFFh	1 MB
0b’100	None	0	0 MB
0b’101	Top 1/2 array	400000h-7FFFFFh	4 MB
0b’110	Top 1/4 array	600000h-7FFFFFh	2 MB
0b’111	Top 1/8 array	700000h-7FFFFFh	1 MB

Half Sleep mode supports putting the device in an ultra-low power state, while the stored data is retained. Half Sleep Mode Entry is entered by writing 0xF0 into Register MR6. CE# going high initiates the Half Sleep mode and must be maintained for the minimum duration of t_HS (minimum Half Sleep duration). Half Sleep Exit is initiated by a low-pulsed CE#.

Deep Power Down (DPD) mode supports putting the device into power down state. DPD Entry is entered by writing 0xC0 into Register MR6. CE# going high initiates the DPD mode and must be maintained for the minimum duration of t_DPD (minimum Deep Power Down duration). DPD Exit is initiated by a low-pulsed CE#. Register values and memory content are not retained in DPD mode. Afterwards, the DPD mode register values will be reset to defaults. t_DPDp is minimum period between two DPD modes (measured from DPD Exit to the next DPD Entry) as well as from the initial power-up to the first DPD Entry.

Registers

MR0

Name: Mode Register 0
Description: Mode Register
Base Address: OSPI_XIP_BASE_ADDRESS
Offset: 0x00
Reset value: 0x09

表 25 MR0 Register
Bits	Field Name	RW	Reset	Description
7:6	FX	RW	0x0	Fixed
5	RD_LT	RW	0x0	Read latency type Value: 0x0: Variable (default) 0x1: Fixed
4:2	RD_LC	RW	0x2	Read latency code When MR0[5] = 0, the latency value and max push out value for each bit of MR0[4:2] are listed below. 0x0: 3, 6 0x1: 4, 8 0x2: 5 (default), 10 0x3: 6, 12 0x4: 7, 14 Others: None When MR0[5] = 1, the latency value for each bit of MR0[4:2] is listed below. 0x0: 6 0x1: 8 0x2: 10 0x3: 12 0x4: 14 Others: None The standard/extended Max. Input CLK Freq (MHz) value for each bit of MR0[4:2] is listed below. 0x0: 66 0x1: 109 0x2: 133 0x3: 166 0x4: 200 Others: None
1:0	DS	RW	0x1	Drive Strength Value: 0x0: Full (25 Ω) 0x1: Half (50 Ω, default) 0x2: 1/4 (100 Ω) 0x3: 1/8 (200 Ω)

MR1

Name: Mode Register 1
Description: Mode Register
Base Address: OSPI_XIP_BASE_ADDRESS
Offset: 0x01
Reset Value: 0x8D

表 26 MR1 Register
Bits	Field Name	RW	Reset	Description
7	ULP	R	0x0	Ultra Low Power Device Value: 0x0: Non-ULP (no Half Sleep) 0x1: ULP (Half Sleep supported)
6:5	RSVD	R		Reserved bits
4:0	VID	R	0x2	Vendor ID 0xD: APM

MR2

Name: Mode Register 2
Description: Mode Register
Base Address: OSPI_XIP_BASE_ADDRESS
Offset: 0x02
Reset Value: 0x93

表 27 MR2 Register
Bits	Field Name	RW	Reset	Description
7	GB	R	0x1	Good-Die Value: 0x0: Fail 0x1: Pass
6:5	RSVD	R		Reserved bits
4:3	DID	R	0x2	Device ID 0x0: Generation 1 0x1: Generation 2 0x2: Generation 3 (default) Others: Reserved
2:0	DEV_D	R	0x3	Device Density 0x1: 4 MB 0x3: 8 MB (default) 0x5: 16 MB 0x7: 32 MB Others: Reserved

MR3

Name: Mode Register 3
Description: Mode Register
Base Address: OSPI_XIP_BASE_ADDRESS
Offset: 0x03
Reset Value: 0x80

表 28 MR3 Register
Bits	Field Name	RW	Reset	Description
7	RBX	R	0x1	Row boundary crossing enable Value: 0x0: RBX not supported 0x1: RBX supported via MR8[3] = 1
6	VCC	R	0x0	Operating voltage range Value: 0x0: 1.8 V (default) 0x1: 3 V
5	SRF	R	0x0	Self refresh flag Value: 0x0: Slow refresh (allowed via MR4[3] = 1, otherwise fast refresh) 0x1: Fast refresh
4:0	RSVD	R		Reserved bits

MR4

Name: Mode Register 4
Description: Mode Register
Base Address: OSPI_XIP_BASE_ADDRESS
Offset: 0x04
Reset Value: 0x40

表 29 MR4 Register
Bits	Field Name	RW	Reset	Description
7:5	WR_L	RW	0x2	Write latency The values of write latency and Fmax (MHz) for MR4[7:5] are listed below. 0x0: 3, 66 0x4: 4, 104 0x2: 5 (default), 133 0x6: 6, 166 0x1: 7, 200 Others: reserved, none
4	FX	RW	0x0	Fixed
3	FLUSH_FREQ	RW	0x0	Refresh Frequency Value: 0x0: Fast refresh (default) 0x1: Enable slow refresh when temperature allows
2:0	PASR	RW		Partial array self-refresh Value: Refer to 表 24

MR6

Name: Mode Register 6
Description: Mode Register
Base Address: OSPI_XIP_BASE_ADDRESS
Offset: 0x06
Reset Value: 0x00

表 30 MR6 Register
Bits	Field Name	RW	Reset	Description
7:4	ULP_MODE_SEL	W	0x0	ULP modes selection 0xF: Half Sleep mode 0xC: Deep Power Down mode Others: Reserved
3:0	RSVD	W		Reserved bits

MR8

Name: Mode Register 8
Description: Mode Register
Base Address: OSPI_XIP_BASE_ADDRESS
Offset: 0x08
Reset Value: 0x00

表 31 MR8 Register
Bits	Field Name	RW	Reset	Description
7	FX	RW	0x0	Fixed
6:4	RSVD	R		Reserved bits
3	RBX	RW	0x0	Row Boundary Crossing Read Enable Value: 0x0: Reads stay within the 1K column address space 0x1: Reads cross row at 1K boundaries
2	BT	RW	0x1	Burst Type. Value: Refer to 表 22
1:0	BL	RW	0x1	Burst Length Value: Refer to 表 22

PSRAM

Specifications

Features

Functional Description

Registers

MR0

MR1

MR2

MR3

MR4

MR6

MR8

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