I2S

• The Inter-IC Sound (I2S) bus is a simple three-wire serial bus protocol developed by Philips to transfer stereo audio data. It is used extensively in audio interfaces. It adopts the design of data and clock signal separation, avoiding the distortion induced by time difference.
• The I2S bus has three signals:
  • SCLK: serial clock (also called BCLK. Each SCLK corresponds to each bit of audio data.)
  • WS: word select (also called LRCK. WS is used to switch between the left and right channel data.)
  • SD(SDATA): serial data (MSB → LSB: Data is transmitted from high-bit to low-bit)
• The I2S module of GR5526 adopts the I2S Philips standard (neither MSB justified standard nor LSB justified standard). For instance, when WS is low, the word being transferred is left stereo data; when WS is high, the word being transferred is right stereo data. For standard I2S formats, the MSB of a word is sent one SCLK cycle after a WS change. Serial data sent by the transmitter can be synchronized with either the negative edge or positive edge of the SCLK signal. However, the receiver must latch the serial data on the rising edge of SCLK. The formats (as receiver) are shown in 图 130.

As the frequency of SCLK is up to 3072 kHz, the number of SCLK cycles for which the (WS) line of I2S can be configured as 16 SCLK cycles, 24 SCLK cycles, or 32 SCLK cycles. If the 16 SCLK cycles are selected, the sampling rate is up to 96 kHz. The calculation formula is as follows:

• Sampling rate = Frequency of SCLK/[2 x Sampling depth (16,24 or 32)]
• Sampling rate = Frequency of WS

Before configuring the I2S module functions, the pin mux of four I2S interface GPIOs must be configured as I2S_M_SCLK (or I2S_S_SCLK), I2S_M_WS (or I2S_S_WS), I2S_M_SDI (or I2S_S_SDI), and I2S_M_SDO (or I2S_S_SDO).

The I2S module can be used as a master or slave. The instance of master mode is I2S_M, and the instance of slave mode is I2S_S. When configured as a master, I2S controller initializes the WS signal and supplies the clock gating and clock enabling signals. Otherwise, when configured as a slave, I2S controller responds to externally generated SCLK and WS signals. When the I2S mode works in master mode, I2S clock generation must be enabled by setting the Clock Enable Register(CER) bit 0 to ‘1’.

If the I2S module is used as master, the I2S Clock Configure Register (CLK_CFG) should be properly configured. The value of bit0~bit11 (div) is decided by the sampling rate, sampling depth (16, 24, or 32) and clock divider source (bit18). For example, if the CLK_CFG’s bit18 is ‘1’ (32 MHz) and the sampling rate is 48 kHz, the calculation formula is as follows:

div_TEMP0 = 32MHz *10/ (2 X Sampling Depth X Sample Rate)
if ((div_TEMP0 % 10) >=5)
{
div_TEMP1 = div_TEMP0 /10 +1;
}
else
{div_TEMP1 = div_TEMP0 /10;
}
if (div_TEMP1>= 2)
{
div = div_TEMP1: 2;
}
else
{
div = 0;
}

You must enable the I2S controller before any data can be received or transmitted from or into the FIFOs. To enable the component, set the I2S enable (I2S_EN) bit of the I2S Enable Register (EN) to 1. When you disable the module, it acts as a global disable. To disable I2S controller, set EN[0] to 0.

After disable, the following events occur:

• TX and RX FIFOs are cleared, and read/write pointers are reset.
• Any data being transmitted or received is lost.
• All other programmable enables (such as transmitter/receiver block enables and individual TX/RX channel enables) in the component are overridden.
• Generation of master mode clock signals sclk_en, ws_out, and sclk_gate are disabled (for instance, they are held low).

When I2S controller is enabled and configured as a master, the device always starts in the left stereo data cycle (WS = 0), and one SCLK cycle after transitions to the right stereo data cycle (WS = 1). This allows for half a frame of SCLKS to write data to the TX FIFOs and to ensure that any connected slave receivers do not miss the start of the data frame (for instance, the WS 1: to-0 transition) once the SCLK restarts. (When I2S controller is configured as a slave, WS is externally supplied.) On reset, the EN[0] is set to 0 (disable).

I2S Master controller and I2S Slave controller support 1 I2S transmit (TX) channel. Stereo data pairs (such as, left and right audio data) written to a TX channel by CPU are shifted out serially on the appropriate serial data out line. The shifting is timed with respect to SCLK and WS.

图 132 illustrates the basic usage flow for an I2S controller when it acts as a transmitter.

I2S Master controller and I2S Slave controller support 1 I2S receive (RX) channel. Stereo data pairs (such as, left and right audio data) are received serially from a data input line. These data words are stored in RX FIFOs until they are read by CPU. The receiving is timed with respect to SCLK and WS.

图 133 illustrates the basic usage flow for an I2S controller when it acts as a receiver.

The I2S module provides two 16-word FIFOs, one for transmission and the other for reception. By configuring the Receive FIFO Configuration Register (RX_FIFO_CFG), you can program the trigger level in the RX FIFO at which the Received Data Available Interrupt is generated. By configuring Transmit FIFO Configuration Register (TX_FIFO_CFG), you can program the trigger level in the TX FIFO at which the Empty Threshold Reached Interrupt is generated. In addition, the Interrupt Mask Register (INT_MASK) is supported to mask TX/RX FIFO overrun and empty interrupts.

The I2S module supports four DMA channels for I2S slave transmit, I2S slave receive, I2S master transmit, and I2S master receive respectively. The Receiver Block DMA Register (RX_DMA), Reset Receiver Block DMA Register (RST_RX_DMA), Transmitter Block DMA Register (TX_DMA), and Reset Transmitter Block DMA Register (RST_TX_DMA) are provided to configure these channels.

• Name: I2S Enable Register
• Description: This register acts as a global enable/disable for I2S.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x0
• Reset Value: 0x00000000

• Name: I2S Receiver Block Enable Register
• Description: This register acts as an enable/disable for the I2S receiver block.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x4
• Reset Value: 0x00000000

• Name: I2S Transmitter Block Enable Register
• Description: This register acts as an enable/disable for the I2S transmitter block.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x8
• Reset Value: 0x00000000

• Name: Clock Enable Register
• Description: This register acts as an enable/disable for the I2S clock generation block.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0xC
• Reset Value: 0x00000000

• Name: Clock Configuration Register
• Description: This register configures the WS when I2S is a master.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x10
• Reset Value: 0x00000000

• Name: Receiver Block FIFO Reset Register
• Description: This register specifies the Receiver Block FIFO Reset Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x14
• Reset Value: 0x00000000

• Name: Transmitter Block FIFO Reset Register
• Description: This register specifies the Transmitter Block FIFO Reset Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x18
• Reset Value: 0x00000000

• Name: Left Receive Buffer Register
• Description: This specifies the Left Receive Buffer Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x20
• Reset Value: 0x00000000

• Name: Left Transmit Holding Register
• Description: This specifies the Left Transmit Holding Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x20
• Reset Value: 0x00000000

• Name: Right Receive Buffer Register
• Description: This specifies the Right Receive Buffer Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x24
• Reset Value: 0x00000000

• Name: Right Transmit Holding Register
• Description: This specifies the Right Transmit Holding Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x24
• Reset Value: 0x00000000

• Name: Receive Enable Register
• Description: This specifies the Receive Enable Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x28
• Reset Value: 0x00000001

• Name: Transmit Enable Register
• Description: This specifies the Transmit Enable Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x2c
• Reset Value: 0x00000001

• Name: Receive Configuration Register
• Description: This specifies the Receive Configuration Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x30
• Reset Value: 0x00000005

• Name: Transmit Configuration Register
• Description: This specifies the Transmit Configuration Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x34
• Reset Value: 0x00000005

• Name: Interrupt status Register
• Description: This specifies the Interrupt Status Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x38
• Reset Value: 0x00000010

• Name: Interrupt Mask Register
• Description: This specifies the Interrupt Mask Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x3c
• Reset Value: 0x00000033

• Name: Receive Overrun Register
• Description: This specifies the Receive Overrun Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x40
• Reset Value: 0x00000000

• Name: Transmit Overrun Register
• Description: This specifies the Transmit Overrun Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x44
• Reset Value: 0x00000000

• Name: Receive FIFO Configuration Register
• Description: This specifies the Receive FIFO Configuration Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x48
• Reset Value: 0x00000008

• Name: Transmit FIFO Configuration Register
• Description: This specifies the Transmit FIFO Configuration Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x4c
• Reset Value: 0x00000008

• Name: Receive FIFO Flush Register
• Description: This specifies the Receive FIFO Flush Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x50
• Reset Value: 0x00000000

• Name: Transmit FIFO Flush Register
• Description: This specifies the Transmit FIFO Flush Register.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x54
• Reset Value: 0x00000000

• Name: Receiver Block DMA Register
• Description: The RX_DMA register allows access to receive channel via a single point rather than through the LEFT_RX_BUF and RIGHT_RX_BUF registers. The receive channel is targeted in a cyclical fashion (starting at the lowest numbered enabled channel) and takes two reads (left and right stereo data) before the component points to the next channel.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x1c0
• Reset Value: 0x00000000

• Name: Reset Receiver Block DMA Register
• Description: The RX_DMA can be reset to the enabled channel via the RST_RX_DMA register. The RST_RX_DMA register can be written to at any stage of the RX_DMA's read cycle; however, it has no effect when the component is in the middle of a stereo pair read.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x1c4
• Reset Value: 0x00000000

• Name: Transmitter Block DMA Register
• Description: The TX_DMA register functions in a similar way to the RX_DMA register and allows write accesses to all of the enabled transmit channels via a single point rather than through the LEFT_TX_HDG and RIGHT_TX_HDG registers.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x1c8
• Reset Value: 0x00000000

• Name: Reset Transmitter Block DMA Register
• Description: This register provides the same functionality as the RST_RX_DMA register but targets TX_DMA instead.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x1cc
• Reset Value: 0x00000000

• Name: I2S Clock Configure Register
• Description: This register is used to configure I2S master clock.
• Base Address: 0x4000F200 (master) and 0x4000F000 (slave)
• Offset: 0x268
• Reset Value: 0x00040008