I2C

Introduction

The Inter-Integrated Circuit (I2C) bus is a two-wire serial interface that is widely used for low-speed communication between chipsets in a system. Using I2C, a microcontroller can communicate with peripherals such as sensors, data converters, and I/O interfaces.

GR5526 SoC has six I2C module instances: I2C0, I2C1, I2C2, I2C3, I2C4, and I2C5 that can be configured as either Master or Slave.

Main Features

The two-wire I2C serial interface consists of a serial data line (SDA) and a serial clock line (SCL) that support:

Standard Mode (up to 100 kbit/s)
Fast Mode (up to 400 kbit/s)
Fast Plus Mode (up to 1000 kbit/s)
High-speed Mode (up to 3.4 Mbit/s)
Clock synchronization
Master or Slave I2C operation
7-bit or 10-bit addressing
Mixed 7-bit and mixed 10-bit format transfer
Transmit and receive FIFO depth at 32 bytes
Interrupt or polled-mode operation
Simple software interface
DMA support

Functional Description

The I2C Controller is made up of an APB slave interface, an I2C interface, and FIFO logic to maintain consistency between the two interfaces, as well as DMA and interrupt logics. A simplified block diagram is illustrated in 图 45.

The following list describes each of the major blocks shown above.

AMBA Bus Interface Unit connects to APB bus.
Register File contains configuration registers and is the interface with software.
Slave State Machine follows the protocol for a slave and monitors bus for address match.
Master State Machine generates the I2C protocol for the master transfers.
Clock Generator produces the required timing to do the following:
- Generate the SCL clock when configured as a master.
- Check for bus idle.
- Generate a START and a STOP.
- Set up the data and hold the data.
RX Shift takes data into the design and extracts it in byte format.
TX Shift presents data supplied by GPU for transfer on the I2C bus.
RX Filter detects the events in the bus; for example, start, stop, and arbitration lost.
Toggle generates pulses on both sides and toggles to transfer signals across clock domains.
Synchronizer transfers signals from one clock domain to another.
DMA Interface generates handshaking signals to the central DMA controller in order to automate the data transfer without CPU intervention.
Interrupt Controller generates raw interrupt and interrupt flags, allowing them to be set and cleared.
RX FIFO/TX FIFO holds the RX FIFO and TX FIFO register banks and controllers, along with their status levels.

I2C Operation

The I2C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only when the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain or open-collector to perform wired-AND functions on the bus. The maximum number of devices on the bus is limited by only the maximum capacitance specification of 400 pF. Data is transmitted in byte packages.

The master is responsible for generating the clock and controlling the transfer of data. The slave is responsible for either transmitting or receiving data to/from the master. The acknowledgement of data is sent by the device that is receiving data, which can be either a master or a slave. The I2C protocol also allows multiple masters to reside on the I2C bus and uses an arbitration procedure to determine the bus ownership.

When a master wants to communicate with a slave, the master transmits a START/RESTART condition that is then followed by the slave address and a control bit ( $R / \bar{W}$ ) to determine if the master wants to transmit data to or receive data from the slave. The slave then sends an acknowledge (ACK) pulse after the address.

If the master (master-transmitter) is writing to the slave (slave-receiver), the receiver gets one byte of data. This transaction continues until the master terminates the transmission with a STOP condition. If the master is reading from a slave (master-receiver), the slave transmits (slave-transmitter) a byte of data to the master, and the master then acknowledges the transaction with the ACK pulse. This transaction continues until the master terminates the transmission by not acknowledging (NACK) the transaction after the last byte is received, and then the master issues a STOP condition or addresses another slave after issuing a RESTART condition. This behavior is illustrated in 图 46.

Note that, I2C block should only be set to operate as an I2C master or an I2C slave, but not both simultaneously. This is achieved by ensuring that bit 0 and bit 6 of the I2C Control Register (CTRL) are never set to 0 and 1, respectively.

START and STOP Conditions

When I2C operates as a master (writing 1 to CTRL[0], and writing 1 to CTRL[6]), putting data into the transmit FIFO causes the I2C block to generate a START condition on the I2C bus. Writing 1 to DATA_CMD[9] causes the I2C block to generate a STOP condition on the I2C bus; a STOP condition is not issued if this bit is not set, even if the transmit FIFO is empty. This behavior is illustrated as follows.

When operating as a slave (writing 0 to CTRL[0], and writing 0 to CTRL[6]), I2C block does not generate START and STOP conditions, as per the protocol. However, if a read request is made to the I2C block, it holds the SCL line low until read data has been supplied to it. This stalls the I2C bus until read data is provided to the slave I2C block, or the I2C block slave is disabled by writing 0 to I2C ENABLE Register (EN[0]). When the bus is idle, both the SCL and SDA signals are pulled high through external pull-up resistors on the bus. When a master wants to start a transmission on the bus, the master issues a START condition. This is defined as a high-to-low transition of the SDA signal while SCL is high. When a master wants to terminate the transmission, the master issues a STOP condition. This is defined as a low-to-high transition of the SDA line while SCL is high. 图 48 shows the timing of the START and STOP conditions. When data is being transmitted on the bus, the SDA line must be stable when the SCL is high.

图 48 Timing of START and STOP conditions

Addressing Slave

There are two address formats: the 7-bit address format and the 10-bit address format. The I2C block supports mixed formats of read and write transactions in 7-bit or 10-bit addressing modes. The I2C block does not support mixed address or mixed address format, that is, a 7-bit address transaction followed by a 10-bit address transaction or vice versa (combined format transactions).

To initiate combined format transfers, CTRL[5] should be enabled. With this value set and operating as a master, when the I2C block completes an I2C transfer, it checks the transmit FIFO and executes the next transfer. If the direction of this transfer differs from the previous transfer, the combined format is used to issue the transfer. If the transmit FIFO is empty when the current I2C transfer completes, a STOP is issued and the next transfer is issued following a START condition.

7-bit Address Format

Using the 7-bit address format, users should write 0 to CTRL[3] and the slave address is stored at I2C Slave Address Register (S_ADDR[6:0]). The first seven bits (bits 7:1) of the first byte set the slave address and the least significant bit (bit 0) (LSB) is the R/W bit as shown in 图 49. When bit 0 ( $R / \bar{W}$ ) is set to 0, the master writes to the slave. When bit 0 ( $R / \bar{W}$ ) is set to 1, the master reads from the slave.

10-bit Address Format

Using the 10-bit address format, users should write 1 to CTRL[3] and the slave address is stored at I2C Slave Address Register (S_ADDR[9:0]). Two bytes are transferred to set the 10-bit address. The transfer of the first byte contains the following bit definition. The first five bits (bits 7:3) notify the slave that this is a 10-bit transfer followed by the next two bits (bits 2:1), which set the slave address (bits 9:8), and the LSB bit (bit 0) is the $R / \bar{W}$ bit. The second byte transferred sets bits 7:0 of the slave address.

图 50 shows the 10-bit address format.

表 252 defines the special purpose and reserved first byte addresses.

表 252 I2C definition of bits in first byte
Slave Address	R/W Bit	Description
0000 000	0	General Call Address. DW_apb_i2c places the data in the receive buffer and issues a General Call interrupt.
0000 000	1	START byte
0000 001	X	CBUS address. I2C ignores these accesses.
0000 010	X	Reserved
0000 011	X	High-speed master code
1111 1XX	X	Reserved
1111 0XX	X	10-bit slave addressing
0001 000	X	SMBus Host
0001 100	X	SMBus Alert Response Address
1100 001	X	SMBus Device Default Address

Transmitting and Receiving

A master can initiate data transmission and reception to/from the bus, acting as either a master-transmitter or master-receiver. A slave responds to requests from the master to either transmit data or receive data to/from the bus, acting as either a slave-transmitter or slave-receiver, respectively.

Master-Transmitter and Slave-Receiver

All data is transmitted in byte format, with no limit on the number of bytes transferred per data transfer. After the master sends the address and $R / \bar{W}$ bit or the master transmits a byte of data to the slave, the slave-receiver must respond with the ACK signal. When a slave-receiver does not respond with an ACK pulse, the master aborts the transfer by issuing a STOP condition. The slave must leave the SDA line high so that the master can abort the transfer.

If the master-transmitter is transmitting data as shown in 图 51, the slave-receiver responds to the master-transmitter with an ACK pulse after every data byte is received.

Master-Receiver and Slave-Transmitter

If the master is receiving data as shown in 图 52, the master responds to the slave-transmitter with an ACK pulse after a byte of data has been received, except for the last byte. This is the way in which the master-receiver notifies the slave-transmitter that this is the last byte. The slave-transmitter relinquishes the SDA line after detecting the No Acknowledge (NACK) so that the master can issue a STOP condition.

When a master does not want to relinquish the bus with a STOP condition, the master can issue a RESTART condition. This is identical to a START condition except it occurs after the ACK pulse. Operating in master mode, the I2C block can then communicate with the same slave using a transfer of a different direction.

Bus Clear Feature

I2C block supports the bus clear feature that provides graceful recovery of data (SDA) and clock (SCL) lines during unlikely events in which either the clock or data line is stuck at low.

SDA Line Stuck at Low Recovery

In cast of SDA line stuck at low, master performs the following actions to recover as shown in 图 53.

Master sends a maximum of 9 clock pulses to recover the bus low within those 9 clocks.
- The number of clock pulses will vary with the number of bits that remain to be sent by the slave. As the maximum number of bits is 9, master sends up to 9 clock pluses and allows the slave to recover it.
- The master attempts to assert a Logic 1 on the SDA line and check whether SDA is recovered. If the SDA is not recovered, it will continue to send a maximum of 9 SCL clocks.
If SDA line is recovered within 9 clock pulses, then the master will send the STOP to release the bus.
If SDA line is not recovered even after 9th clock pulse, then the system needs a hardware reset.

The detailed flow to recover the SDA stuck at LOW is shown in 图 54.

SCL Line Stuck at Low Recovery

In the unlikely event (due to an electric failure of a circuit) where the clock (SCL) is stuck at LOW, there is no effective method to overcome this problem but to reset the bus using the hardware reset signal. The detailed flow to recover the SCL stuck at LOW is shown in 图 54.

图 54 Flowchart for SCL and SDA bus recovery

SDA Hold Time

The I2C protocol specification requires 300 ns of hold time on the SDA signal (t_{HD_DAT}, SDA hold time, see 图 57 in standard mode and fast mode, and a hold time long enough to bridge the undefined part between logic 1 and logic 0 of the falling edge of SCL in high speed mode and fast mode plus.

Board delays on the SCL and SDA signals can mean that the hold-time requirement is met at the I2C master, but not at the I2C slave (or vice versa). As each application encounters differing board delays, the I2C block contains a software programmable register (SDA_HOLD) to enable dynamic adjustment of the SDA hold time.

SDA_HOLD[15:0] are used to control the hold time of SDA during transmit in both slave and master mode (After SCL goes from HIGH to LOW).

SDA_HOLD[23:16] are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver (in either master or slave mode).

If different SDA hold times are required for different speed modes, the SDA_HOLD register must be reprogrammed when the speed mode is being changed. The SDA_HOLD register can be programmed only when the DW_apb_i2c is disabled (EN[0] = 0).

SDA Hold Timings in Receiver

When I2C block acts as a receiver, according to the I2C protocol, the device should internally hold the SDA line to bridge undefined gap between logic 1 and logic 0 of SCL.

SDA_HOLD[23:16] can be used to alter the internal hold time which I2C block applies to the incoming SDA line. Each value in the SDA_HOLD[23:16] represents a unit of one sclk (in serial clock implementation) period. The minimum value of SDA_HOLD[23:16] is 0. This hold time is applicable only when SCL is HIGH. The receiver does not extend the SDA after SCL goes LOW internally. 图 55 shows the I2C block as receiver with SDA_HOLD[23:16] being programmed to greater than or equal to 3. If SDA_HOLD[23:16] are greater than 3, I2C block does not hold SDA beyond 3 sclk cycles, because SCL goes low internally.

图 55 I2C block as receiver with SDA hold time

The maximum values of SDA_HOLD[23:16] that can be programmed in the register for the respective speed modes are derived from the equations shown in the table below.

表 253 Maximum values for SDA_HOLD[23:16]
Speed Mode	Maximum SDA_HOLD[23:16] Value
Standard Mode	SS_CLK_HCNT[15:0] – FS_SPKLEN[7:0] -3
Fast Mode or Fast Mode Plus	FS_CLK_HCNT[15:0] – FS_SPKLEN[7:0] -3
High Speed	Min{FS_CLK_HCNT[15:0] – FS_SPKLEN[7:0] -3, HS_CLK_HCNT[15:0] – HS_SPKLEN[7:0] -3}

SDA Hold Timings in Transmitter

The SDA_HOLD [15:0] can be used to alter the timing of the generated SDA (data_oe, see 图 56) signal by the I2C block. Each value in the SDA_HOLD [15:0] represents a unit of one sclk period.

When the I2C block is operating in master mode, the minimum t_{HD_DAT} timing is one ic_clk period. Therefore even when SDA_TX_HOLD has a value of zero, the I2C block drives SDA (data_oe) one sclk cycle after driving SCL (scl_oe) to logic 0. For all other values of SDA_HOLD[15:0], drive on SDA (data_oe) occurs SDA_HOLD[15:0] sclk cycles after driving SCL (scl_oe) to logic 0.

When the I2C block is operating in slave mode, the minimum t_{HD_DAT} timing is SPKLEN + 7 sclk periods, where SPKLEN is FS_SPKLEN[7:0] (operating in standard mode, fast mode, or fast mode plus) or HS_SPKLEN[7:0] (operating in high speed mode).

This delay allows for synchronization and spike suppression on the SCL sample. Therefore, even when SDA_HOLD[15:0] has a value less than SPKLEN + 7, the I2C block drives SDA (data_oe) SPKLEN + 7 ic_clk cycles after SCL (scl_oe) has transitioned to logic 0. For all other values of SDA_HOLD[15:0], drive on SDA occurs SDA_HOLD[15:0] sclk cycles after SCL has transitioned to logic 0.

图 56 I2C Master implementing tHD_DAT with SDA_HOLD[15:0] = 3

When the I2C block is operating in Slave Mode, the minimum t_{HD_DAT} timing is SPKLEN + 7 sclk periods, where SPKLEN is FS_SPKLEN[7:0] (operating in standard mode, fast mode, or fast mode plus) or HS_SPKLEN[7:0] (operating in high speed mode).

Registers

CTRL

Name: I2C Control Register
Description: This register can be written only when the I2C is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.
Base Address: 0x4000C300 + x*0x100
Offset: 0x00
Reset Value: 0x0000007F

表 254 I2C Control Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R		Reserved bits
11	BUS_CLEAR_FEATURE_CTRL	RW	0x0	In Master mode Value: 0x1: Bus Clear Feature is enabled. 0x0: Bus Clear Feature is disabled.
10	STOP_DET_M_ACTIVE	RW	0x0	In Master mode Value: 0x1: Issues the STOP_DET interrupt only when master is active. 0x0: Issues the STOP_DET irrespective of whether master is active or not.
9	RX_FIFO_FULL_HLD_CTRL	RW	0x0	This bit controls whether I2C should hold the bus when the RX FIFO is physically full. Value: 0x1 (ENABLED): Hold bus when RX_FIFO is full. 0x0 (DISABLED): Overflow when RX_FIFO is full.
8	TX_EMPTY_CTRL	RW	0x0	This bit controls the generation of the TX_EMPTY interrupt, as described in the RAW_INT_STAT register. Value: 0x0 (DISABLED): Default behavior of TX_EMPTY interrupt. 0x1 (ENABLED): Controlled generation of TX_EMPTY interrupt.
7	STOP_DET_INT	RW	0x0	In slave mode Value: 0x0: Issues the STOP_DET irrespective of whether it is addressed or not. 0x1: Issues the STOP_DET interrupt only when it is addressed. Note: During a general call address, the slave does not issue the STOP_DET interrupt if STOP_DET_INT = 1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (S_ADDR).
6	S_DIS	RW	0x1	This bit controls whether I2C has its slave disabled. By default, the slave is always disabled (in reset state as well). If you need to enable it after reset, set this bit to 0. If this bit is set (slave is disabled), I2C functions only as a master and does not perform any action that requires a slave. Note: Software should ensure that if this bit is written with 0, then bit 0 should also be written with 0. Value: 0x0 (S_EN): Slave mode is enabled. 0x1 (S_DIS): Slave mode is disabled.
5	RESTART_EN	RW	0x1	Determine whether RESTART conditions may be sent when I2C acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several I2C operations. When RESTART is disabled, the master is prohibited from performing the following functions: Performing any high-speed mode operation. Performing direction changes in combined format mode. Performing a read operation with a 10-bit address. By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple I2C transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABORT) of the RAW_INT_STAT register. Value: 0x0 (DISABLED): Master restart disabled. 0x1 (ENABLED): Master restart enabled.
4	ADDR_BIT_M	RW	0x1	This bit controls whether the I2C starts its transfers in 7-bit or 10-bit addressing mode when I2C acts as a master. Value: 0x0 (ADDR_7BITS): Master 7-bit addressing mode 0x1 (ADDR_10BITS): Master 10-bit addressing mode
3	ADDR_BIT_S	RW	0x1	When I2C acts as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses. Value: 0x0 (ADDR_7BITS): Slave 7-Bit addressing 0x1 (ADDR_10BITS): Slave 10-Bit addressing
2:1	SPEED	RW	0x3	These bits control at which speed the I2C operates; its setting is relevant only if one is operating the I2C in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to 3. 0x1: Standard Mode (100 kbit/s) 0x2: Fast Mode ( ≤ 400 kbit/s) or Fast Plus Mode (≤ 1000 kbit/s) 0x3: High-speed Mode (2 Mbit/s) Value: 0x1 (STANDARD): Standard Speed Mode of operation 0x2 (FAST): Fast or Fast Plus Mode of operation 0x3 (HIGH): High-speed Mode of operation
0	M_MODE	RW	0x1	This bit controls whether the I2C master is enabled. Note: Software should ensure that if this bit is written with '1', then bit 6 should also be written with '1'. Value: 0x0 (DISABLED): Master mode is disabled. 0x1 (ENABLED): Master mode is enabled.

TARGET_ADDR

Name: I2C Target Address Register
Description: This register can be written to only when EN[0] is set to 0. You cannot change the TARGET_ADDR address dynamically.

Note:

If the software or application is aware that the I2C is not using the TARGET_ADDR address for the pending commands in the TX FIFO, it is possible to update the TARGET_ADDR address even when the TX FIFO has entries (STAT[2]= 0).

It is not necessary to perform any write to this register if the I2C is enabled as an I2C slave only.

Base address: 0x4000C300 + x*0x100
Offset: 0x04
Reset Value: 0x00000055

表 255 I2C Target Address Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R		Reserved bits
11	SPECIAL	RW	0x0	This bit indicates whether software performs a Device-ID or General Call. Value: 0x0 (DISABLED): Disable programming of GENERAL_CALL or START_BYTE transmission 0x1 (ENABLED): Enable programming of GENERAL_CALL or START_BYTE transmission
10	TX_CTRL	RW	0x0	If bit 11 (SPECIAL) is set to 1, this bit indicates whether a General Call is to be performed by the I2C.
9:0	TARGET	RW	0x55	This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. If the TARGET_ADDR and S_ADDR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to a slave only.

S_ADDR

Name: I2C Slave Address Register
Description: This register sets the address for I2C when it acts as a slave.
Base Address: 0x4000C300 + x*0x100
Offset: 0x08
Reset Value: 0x00000055

表 256 I2C Slave Address Register
Bits	Field Name	RW	Reset	Description
31:10	RSVD	R		Reserved bits
9:0	S_ADDR	RW	0x55	The S_ADDR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only S_ADDR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: 0x00 to 0x07, or 0x78 to 0x7F. The correct operation of the device is not guaranteed if you program the S_ADDR or TARGET_ADDR to a reserved value. Refer to 表 252 for a complete list of these reserved values.

M_HS_ADDR

Name: I2C High-Speed Master Mode Code Address Register
Description: I2C High-Speed Master Mode Code Address Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x0C
Reset Value: 0x00000001

表 257 I2C High-Speed Master Mode Code Address Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2:0	M_HS_ADDR	RW	0x1	This bit field holds the value of the I2C High-speed mode master code. High-speed-mode master codes are reserved 8-bit codes (00001xxx) that are not used for slave addressing or other purposes. Each master has its unique master code; up to eight high-speed mode masters can be present on the same I2C bus system. Valid values are from 0 to 7. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

DATA_CMD

Name: I2C RX/TX Data Buffer and Command Register
Description: This is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.

Note:

In order to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the I2C will stop acknowledging.

Base Address: 0x4000C300 + x*0x100
Offset: 0x10
Reset Value: 0x00000000

表 258 I2C RX/TX Data Buffer and Command Register
Bits	Field Name	RW	Reset	Description
31:11	RSVD	R		Reserved bits
10	RESTART	W	0x0	This bit controls whether a RESTART is issued before the byte is sent or received. Value: 0x0 (DISABLE): Do not issue RESTART before this command 0x1 (ENABLE): Issue RESTART before this command
9	STOP	W	0x0	This bit controls whether a STOP is issued after the byte is sent or received. Value: 0x0 (DISABLE): Do not issue STOP after this command 0x1 (ENABLE): Issue STOP after this command
8	CMD	W	0x0	This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C acts as a slave. It controls only the direction when it acts as a master. Value: 0x0 (WRITE): Master Write command 0x1 (READ): Master Read command
7:0	DATA	RW	0x0	This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DATA) are ignored by the I2C. However, when you read this register, these bits return the value of data received on the I2C interface.

SS_CLK_HCNT

Name: Standard Speed I2C Clock SCL High Count Register
Description: Standard Speed I2C Clock SCL High Count Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x14
Reset Value: 0x00000190

表 259 Standard Speed I2C Clock SCL High Count Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	COUNT	RW	0x0190	This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted, the value will be set to 6. Note: This register must not be programmed to a value higher than 65525, because I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of COUNT + 10.

SS_CLK_LCNT

Name: Standard Speed I2C Clock SCL Low Count Register
Description: Standard Speed I2C Clock SCL Low Count Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x18
Reset Value: 0x000001D6

表 260 Standard Speed I2C Clock SCL Low Count Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	COUNT	RW	0x01D6	This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, the value will be set to 8.

FS_CLK_HCNT

Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
Description: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x1C
Reset Value: 0x0000003C

表 261 Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	COUNT	RW	0x003C	This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted, the value will be set to 6.

FS_CLK_LCNT

Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
Description: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x20
Reset Value: 0x00000082

表 262 Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	COUNT	RW	0x0082	This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, the value will be set to 8.

HS_CLK_HCNT

Name: High Speed I2C Clock SCL High Count Register
Description: High Speed I2C Clock SCL High Count Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x24
Reset Value: 0x00000006

表 263 High Speed I2C Clock SCL High Count Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	COUNT	RW	0x0006	This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. The SCL High time depends on the loading of the bus. For 100 pF loading, the SCL High time is 60 ns; for 400 pF loading, the SCL High time is 120 ns. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted, the value will be set to 6.

HS_CLK_LCNT

Name: High Speed I2C Clock SCL Low Count Register
Description: High Speed I2C Clock SCL Low Count Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x28
Reset Value: 0x00000010

表 264 High Speed I2C Clock SCL Low Count Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	COUNT	RW	0x0010	This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. The SCL low time depends on the loading of the bus. For 100pF loading, the SCL low time is 160 ns; for 400 pF loading, the SCL low time is 320 ns. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, the value will be set to 8.

INT_STAT

Name: I2C Interrupt Status Register
Description: Each bit in this register has a corresponding mask bit in the INT_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the RAW_INT_STAT register.
Base Address: 0x4000C300 + x*0x100
Offset: 0x2C
Reset Value: 0x00000000

表 265 I2C Interrupt Status Register
Bits	Field Name	RW	Reset	Description
31:15	RSVD	R		Reserved bits
14	SCL_STUCK_AT_LOW	R	0x0	See RAW_INT_STAT for a detailed description of SCL_STUCK_AT_LOW bit. Value: • 0x1 (ACTIVE): SCL_STUCK_AT_LOW interrupt is active. • 0x0 (INACTIVE): SCL_STUCK_AT_LOW interrupt is inactive.
13	M_HOLD	R	0x0	See RAW_INT_STAT for a detailed description of M_HOLD bit. Value: 0x0 (INACTIVE): M_HOLD interrupt is inactive. 0x1 (ACTIVE): M_HOLD interrupt is active.
12	RESTART_DET	R	0x0	See RAW_INT_STAT for a detailed description of RESTART_DET bit. Value: 0x0 (INACTIVE): RESTART_DET interrupt is inactive. 0x1 (ACTIVE): RESTART_DET interrupt is active.
11	GEN_CALL	R	0x0	See RAW_INT_STAT for a detailed description of GEN_CALL bit. Value: 0x0 (INACTIVE): GEN_CALL interrupt is inactive. 0x1 (ACTIVE): GEN_CALL interrupt is active.
10	START_DET	R	0x0	See RAW_INT_STAT for a detailed description of START_DET bit. Value: 0x0 (INACTIVE): START_DET interrupt is inactive. 0x1 (ACTIVE): START_DET interrupt is active.
9	STOP_DET	R	0x0	See RAW_INT_STAT for a detailed description of STOP_DET bit. Value: 0x0 (INACTIVE): STOP_DET interrupt is inactive. 0x1 (ACTIVE): STOP_DET interrupt is active.
8	ACTIVITY	R	0x0	See RAW_INT_STAT for a detailed description of ACTIVITY bit. Value: 0x0 (INACTIVE): ACTIVITY interrupt is inactive. 0x1 (ACTIVE): ACTIVITY interrupt is active.
7	RX_DONE	R	0x0	See RAW_INT_STAT for a detailed description of RX_DONE bit. Value: 0x0 (INACTIVE): RX_DONE interrupt is inactive. 0x1 (ACTIVE): RX_DONE interrupt is active.
6	TX_ABORT	R	0x0	See RAW_INT_STAT for a detailed description of TX_ABORT bit. Value: 0x0 (INACTIVE): TX_ABORT interrupt is inactive. 0x1 (ACTIVE): TX_ABORT interrupt is active.
5	RD_REQ	R	0x0	See RAW_INT_STAT for a detailed description of RD_REQ bit. Value: 0x0 (INACTIVE): RD_REQ interrupt is inactive. 0x1 (ACTIVE): RD_REQ interrupt is active.
4	TX_EMPTY	R	0x0	See RAW_INT_STAT for a detailed description of TX_EMPTY bit. Value: 0x0 (INACTIVE): TX_EMPTY interrupt is inactive. 0x1 (ACTIVE): TX_EMPTY interrupt is active.
3	TX_OVER	R	0x0	See RAW_INT_STAT for a detailed description of TX_OVER bit. Value: 0x0 (INACTIVE): TX_OVER interrupt is inactive. 0x1 (ACTIVE): TX_OVER interrupt is active.
2	RX_FULL	R	0x0	See RAW_INT_STAT for a detailed description of RX_FULL bit. Value: 0x0 (INACTIVE): RX_FULL interrupt is inactive. 0x1 (ACTIVE): RX_FULL interrupt is active.
1	RX_OVER	R	0x0	See RAW_INT_STAT for a detailed description of RX_OVER bit. Value: 0x0 (INACTIVE): RX_OVER interrupt is inactive. 0x1 (ACTIVE): RX_OVER interrupt is active.
0	RX_UNDER	R	0x0	See RAW_INT_STAT for a detailed description of RX_UNDER bit. Value: 0x0 (INACTIVE): RX_UNDER interrupt is inactive. 0x1 (ACTIVE): RX_UNDER interrupt is active.

INT_MASK

Name: I2C Interrupt Mask Register
Description: These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.
Base Address: 0x4000C300 + x*0x100
Offset: 0x30
Reset Value: 0x000008FF

表 266 I2C Interrupt Mask Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R		Reserved bits
11	MASK_GEN_CALL	RW	0x1	This bit masks the GEN_CALL interrupt in INT_STAT register. Value: 0x0 (ENABLED): GEN_CALL interrupt is masked. 0x1 (DISABLED): GEN_CALL interrupt is unmasked.
10	MASK_START_DET	RW	0x0	This bit masks the START_DET interrupt in INT_STAT register. Value: 0x0 (ENABLED): START_DET interrupt is masked. 0x1 (DISABLED): START_DET interrupt is unmasked.
9	MASK_STOP_DET	RW	0x0	This bit masks the STOP_DET interrupt in INT_STAT register. Value: 0x0 (ENABLED): STOP_DET interrupt is masked. 0x1 (DISABLED): STOP_DET interrupt is unmasked.
8	MASK_ACTIVITY	RW	0x0	This bit masks the ACTIVITY interrupt in INT_STAT register. Value: 0x0 (ENABLED): ACTIVITY interrupt is masked. 0x1 (DISABLED): ACTIVITY interrupt is unmasked.
7	MASK_RX_DONE	RW	0x1	This bit masks the RX_DONE interrupt in INT_STAT register. Value: 0x0 (ENABLED): RX_DONE interrupt is masked. 0x1 (DISABLED): RX_DONE interrupt is unmasked.
6	MASK_TX_ABORT	RW	0x1	This bit masks the TX_ABORT interrupt in INT_STAT register. Value: 0x0 (ENABLED): TX_ABORT interrupt is masked. 0x1 (DISABLED): TX_ABORT interrupt is unmasked.
5	MASK_RD_REQ	RW	0x1	This bit masks the RD_REQ interrupt in INT_STAT register. Value: 0x0 (ENABLED): RD_REQ interrupt is masked. 0x1 (DISABLED): RD_REQ interrupt is unmasked.
4	MASK_TX_EMPTY	RW	0x1	This bit masks the TX_EMPTY interrupt in INT_STAT register. Value: 0x0 (ENABLED): TX_EMPTY interrupt is masked. 0x1 (DISABLED): TX_EMPTY interrupt is unmasked.
3	MASK_TX_OVER	RW	0x1	This bit masks the TX_OVER interrupt in INT_STAT register. Value: 0x0 (ENABLED): TX_OVER interrupt is masked. 0x1 (DISABLED): TX_OVER interrupt is unmasked.
2	MASK_RX_FULL	RW	0x1	This bit masks the RX_FULL interrupt in INT_STAT register. Value: 0x0 (ENABLED): RX_FULL interrupt is masked. 0x1 (DISABLED): RX_FULL interrupt is unmasked.
1	MASK_RX_OVER	RW	0x1	This bit masks the RX_OVER interrupt in INT_STAT register. Value: 0x0 (ENABLED): RX_OVER interrupt is masked. 0x1 (DISABLED): RX_OVER interrupt is unmasked.
0	MASK_RX_UNDER	RW	0x1	This bit masks the RX_UNDER interrupt in INT_STAT register. Value: 0x0 (ENABLED): RX_UNDER interrupt is masked. 0x1 (DISABLED): RX_UNDER interrupt is unmasked.

RAW_INT_STAT

Name: I2C Raw Interrupt Status Register
Description: Unlike the INT_STAT register, these bits are not masked so they always show the true status of the I2C.
Base Address: 0x4000C300 + x*0x100
Offset: 0x34
Reset Value: 0x00000000

表 267 I2C Raw Interrupt Status Register
Bits	Field Name	RW	Reset	Description
31:15	RSVD	R		Reserved bits
14	RAW_SCL_STUCK_AT_LOW	R	0x0	Indicates whether the SCL Line is stuck at low for the SCL_STUCK_LOW_TIMEOUT number of ic_clk periods Value: 0x0 (ACTIVE): RAW_SCL_STUCK_AT_LOW interrupt is active. 0x1 (ACTIVE): RAW_SCL_STUCK_AT_LOW interrupt is inactive.
13	RAW_M_HOLD	R	0x0	Indicate whether the master is holding the bus and TX FIFO is empty. Value: 0x1 (ACTIVE): RAW_M_HOLD interrupt is active 0x0 (INACTIVE): RAW_M_HOLD interrupt is inactive
12	RAW_RESTART_DET	R	0x0	Indicate whether a RESTART condition has occurred on the I2C interface when I2C is operating in Slave mode and the slave is being addressed. Note: However, in High-speed Mode, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore I2C does not generate the RESTART_DET interrupt. Value: 0x0 (INACTIVE): RAW_RESTART_DET interrupt is inactive 0x1 (ACTIVE): RAW_RESTART_DET interrupt is active
11	RAW_GEN_CALL	R	0x0	Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling I2C or when the CPU reads bit 0 of the CLR_GEN_CALL register. I2C stores the received data in the RX buffer. Value: 0x0 (INACTIVE): RAW_GEN_CALL interrupt is inactive 0x1 (ACTIVE): RAW_GEN_CALL interrupt is active
10	RAW_START_DET	R	0x0	Indicate whether a START or RESTART condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode. Value: 0x0 (INACTIVE): RAW_START_DET interrupt is inactive 0x1 (ACTIVE): RAW_START_DET interrupt is active
9	RAW_STOP_DET	R	0x0	Indicate whether a STOP condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode. In Slave Mode: If CTRL[7] = 0x1 (STOP_DET_INT), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_INT = 0x1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (S_ADDR). If CTRL[7] = 0x0 (STOP_DET_INT), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: If CTRL[10] = 0x1, the STOP_DET interrupt will be issued only if Master is active. If CTRL[10] = 0x0, the STOP_DET interrupt will be issued irrespective of whether master is active or not. Value: 0x0 (INACTIVE): RAW_STOP_DET interrupt is inactive. 0x1 (ACTIVE): RAW_STOP_DET interrupt is active.
8	RAW_ACTIVITY	R	0x0	This bit captures I2C activity and stays set until it is cleared. There are four ways to clear it: Disabling the I2C Reading the CLR_ACTIVITY register Reading the CLR_INT register System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the I2C module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Value: 0x0 (INACTIVE): RAW_ACTIVITY interrupt is inactive. 0x1 (ACTIVE): RAW_ACTIVITY interrupt is active.
7	RAW_RX_DONE	R	0x0	When the I2C is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Value: 0x0 (INACTIVE): RAW_RX_DONE interrupt is inactive. 0x1 (ACTIVE): RAW_RX_DONE interrupt is active.
6	RAW_TX_ABORT	R	0x0	This bit indicates if I2C, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the TX_ABORT_SRC register indicates the reason why the transmit abort takes place. Note: The I2C flushes/resets/empties only the TX_FIFO whenever there is a transmit abort caused by any of the events tracked by the TX_ABORT_SRC register. The TX FIFO remains in this flushed state until the register CLR_TX_ABORT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. Value: 0x0 (INACTIVE): RAW_TX_ABORT interrupt is inactive. 0x1 (ACTIVE): RAW_TX_ABORT interrupt is active.
5	RAW_RD_REQ	R	0x0	This bit is set to 1 when I2C is acting as a slave and another I2C master is attempting to read data from I2C. The I2C holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the DATA_CMD register. This bit is set to 0 just after the processor reads the CLR_RD_REQ register. Value: 0x0 (INACTIVE): RAW_RD_REQ interrupt is inactive. 0x1 (ACTIVE): RAW_RD_REQ interrupt is active.
4	RAW_TX_EMPTY	R	0x0	The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the CTRL register. When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_FIFO_THD register. When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_FIFO_THD register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When EN[0] is set to 0, the TX FIFO is flushed and held in reset. Therefore, the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is any activity in the master or slave state machines. When there is no longer any activity, then with EN[0] = 0, this bit is set to 0. Value: 0x0 (INACTIVE): RAW_TX_EMPTY interrupt is inactive. 0x1 (ACTIVE): RAW_TX_EMPTY interrupt is active.
3	RAW_TX_OVER	R	0x0	Set during transmit if the transmit buffer is filled to 8 and the processor attempts to issue another I2C command by writing to the DATA_CMD register. When I2C module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when EN[0] goes to 0, this interrupt is cleared. Value: 0x0 (INACTIVE): RAW_TX_OVER interrupt is inactive 0x1 (ACTIVE): RAW_TX_OVER interrupt is active
2	RAW_RX_FULL	R	0x0	Set when the receive buffer reaches or goes above the RX_FIFO_THD threshold in the RX_FIFO_THD register. It is automatically cleared by hardware when buffer level goes below the threshold. If I2C module is disabled (EN[0] = 0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the EN bit 0 is programmed with a 0, regardless of the activity that continues. Value: 0x0 (INACTIVE): RAW_RX_FULL interrupt is inactive. 0x1 (ACTIVE): RAW_RX_FULL interrupt is active.
1	RAW_RX_OVER	R	0x0	Set if the receive buffer is completely filled to 8 and an additional byte is received from an external I2C device. The I2C acknowledges this, but any data bytes received after the FIFO is full are lost. If I2C module is disabled (EN[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when EN[0] goes to 0, this interrupt is cleared. Value: 0x0 (INACTIVE): RAW_RX_OVER interrupt is inactive. 0x1 (ACTIVE): RAW_RX_OVER interrupt is active.
0	RAW_RX_UNDER	R	0x0	Set if the processor attempts to read the receive buffer when it is empty by reading from the DATA_CMD register. If the module is disabled (EN[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when EN[0] goes to 0, this interrupt is cleared. Value: 0x0 (INACTIVE): RAW_RX_UNDER interrupt is inactive. 0x1 (ACTIVE): RAW_RX_UNDER interrupt is active.

RX_FIFO_THD

Name: I2C Receive FIFO Threshold Register
Description: I2C Receive FIFO Threshold Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x38
Reset Value: 0x00000000

表 268 I2C Receive FIFO Threshold Register
Bits	Field Name	RW	Reset	Description
31:8	RSVD	R		Reserved bits
7:0	THD	RW	0x00	Receive FIFO Threshold Level. Control the level of entries (or above) that triggers the RAW_RX_FULL interrupt (bit 2 in RAW_INT_STAT register). The valid range is 0–255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.

TX_FIFO_THD

Name: I2C Transmit FIFO Threshold Register
Description: I2C Transmit FIFO Threshold Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x3C
Reset Value: 0x00000000

表 269 I2C Transmit FIFO Threshold Register
Bits	Field Name	RW	Reset	Description
31:8	RSVD	R		Reserved bits
7:0	THD	RW	0x00	Transmit FIFO Threshold Level. Control the level of entries (or below) that trigger the RAW_TX_EMPTY interrupt (bit 4 in RAW_INT_STAT register). The valid range is 0–255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.

CLR_INT

Name: Clear Combined and Individual Interrupt Register
Description: Clear Combined and Individual Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x40
Reset Value: 0x00000000

表 270 Clear Combined and Individual Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_INT	R	0x0	Read this register to clear the combined interrupt, all individual interrupts, and the TX_ABORT_SRC register. This bit does not clear hardware clearable interrupts but software clearable interrupts.

CLR_RX_UNDER

Name: Clear RX_UNDER Interrupt Register
Description: Clear RX_UNDER Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x44
Reset Value: 0x00000000

表 271 Clear RX_UNDER Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_RX_UNDER	R	0x0	Read this register to clear the RAW_RX_UNDER interrupt (bit 0) of the RAW_INT_STAT register.

CLR_RX_OVER

Name: Clear RX_OVER Interrupt Register
Description: Clear RX_OVER Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x48
Reset Value: 0x00000000

表 272 Clear RX_OVER Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_RX_OVER	R	0x0	Read this register to clear the RAW_RX_OVER interrupt (bit 1) of the RAW_INT_STAT register.

CLR_TX_OVER

Name: Clear TX_OVER Interrupt Register
Description: Clear TX_OVER Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x4C
Reset Value: 0x00000000

表 273 Clear TX_OVER Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_TX_OVER	R	0x0	Read this register to clear the RAW_TX_OVER interrupt (bit 3) of the RAW_INT_STAT register.

CLR_RD_REQ

Name: Clear RD_REQ Interrupt Register
Description: Clear RD_REQ Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x50
Reset Value: 0x00000000

表 274 Clear RD_REQ Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_RD_REQ	R	0x0	Read this register to clear the RAW_RD_REQ interrupt (bit 5) of the RAW_INT_STAT register.

CLR_TX_ABORT

Name: Clear TX_ABORT Interrupt Register
Description: Clear TX_ABORT Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x54
Reset Value: 0x00000000

表 275 Clear TX_ABORT Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_TX_ABORT	R	0x0	Read this register to clear the RAW_TX_ABORT interrupt (bit 6) of the RAW_INT_STAT register, and the TX_ABORT_SRC register.

CLR_RX_DONE

Name: Clear RX_DONE Interrupt Register
Description: Clear RX_DONE Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x58
Reset Value: 0x00000000

表 276 Clear RX_DONE Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_RX_DONE	R	0x0	Read this register to clear the RAW_RX_DONE interrupt (bit 7) of the RAW_INT_STAT register.

CLR_ACTIVITY

Name: Clear ACTIVITY Interrupt Register
Description: Clear ACTIVITY Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x5C
Reset Value: 0x00000000

表 277 Clear ACTIVITY Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_ACTIVITY	R	0x0	Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the RAW_ACTIVITY interrupt (bit 8) of the RAW_INT_STAT register.

CLR_STOP_DET

Name: Clear STOP_DET Interrupt Register
Description: Clear STOP_DET Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x60
Reset Value: 0x00000000

表 278 Clear STOP_DET Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_STOP_DET	R	0x0	Read this register to clear the RAW_STOP_DET interrupt (bit 9) of the RAW_INT_STAT register.

CLR_START_DET

Name: Clear START_DET Interrupt Register
Description: Clear START_DET Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x64
Reset Value: 0x00000000

表 279 Clear START_DET Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_START_DET	R	0x0	Read this register to clear the RAW_START_DET interrupt (bit 10) of the RAW_INT_STAT register.

CLR_GEN_CALL

Name: Clear GEN_CALL Interrupt Register
Description: Clear GEN_CALL Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0x68
Reset Value: 0x00000000

表 280 Clear GEN_CALL Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_GEN_CALL	R	0x0	Read this register to clear the RAW_GEN_CALL interrupt (bit 11) of RAW_INT_STAT register.

EN

Name: I2C ENABLE Register
Description: I2C enable register
Base Address: 0x4000C300 + x*0x100
Offset: 0x6C
Reset Value: 0x00000000

表 281 I2C ENABLE Register
Bits	Field Name	RW	Reset	Description
31:4	RSVD	R		Reserved bits
3	SDA_STUCK_RECOVERY_ENABLE	RW	0x0	If SDA is stuck at low, which is indicated by the TX_ABORT interrupt (TX_ABORT_SRC[17]), this bit is used as a control knob to initiate the SDA Recovery Mechanism (that is, send at most 9 SCL clocks and STOP to release the SDA line) and then this bit gets auto clear. Value: • 0x1 (SDA_STUCK_RECOVERY_ENABLED): Master initiates the SDA stuck at low recovery mechanism. • 0x0 (SDA_STUCK_RECOVERY_DISABLED): Master disables the SDA stuck at low recovery mechanism.
2	TX_CMD_BLOCK	RW	0x0	In Master mode: Value: 0x0 (NOT_BLOCKED): TX Command execution not blocked 0x1 (BLOCKED): TX Command execution blocked
1	ABORT	RW	0x0	When set, the controller initiates the transfer abort. The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when EN is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the TX FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. Value: 0x0 (DISABLED): ABORT operation not in progress 0x1 (ENABLED): ABORT operation in progress
0	ACTIVITY	RW	0x0	Control whether the I2C is enabled. Software can disable I2C while it is active. However, it is important that care should be taken to ensure that I2C is disabled properly. When I2C is disabled, the following occurs: The TX FIFO and RX FIFO get flushed. Status bits in the INT_STAT register are still active until I2C goes into IDLE state. If the I2C module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is completed. If the module is receiving, the I2C stops the current transfer at the end of the current byte and does not acknowledge the transfer. Value: 0x0 (DISABLED): I2C is disabled. 0x1 (ENABLED): I2C is enabled.

STAT

Name: I2C STATUS Register
Description: This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register requests an interrupt.
When the I2C is disabled by writing 0 in Bit 0 of the EN register:
- Bits 1 and 2 are set to 1
- Bits 3 and 6 are set to 0
- When the master or slave state machine goes idle and EN[0]=0:
- Bits 5 and 6 are set to 0
Base Address: 0x4000C300 + x*0x100
Offset: 0x70
Reset Value: 0x00000006

表 282 I2C STATUS Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R		Reserved bits
11	SDA_STUCK_NOT_RECOVERED	R	0x0	This bit indicates that SDA stuck at low is not recovered after the recovery mechanism. In Slave mode, this register bit is not applicable. Value: 0x1 (ACTIVE): SDA Stuck at low is recovered after recovery mechanism. 0x0 (INACTIVE): SDA Stuck at low is not recovered after recovery mechanism.
10:7	RSVD	R		Reserved bits
6	S_ACTIVITY	R	0x0	Slave Activity Status. When the Slave is not in the IDLE state, this bit is set. Value: 0x0 (INACTIVE): Slave is idle. 0x1 (ACTIVE): Slave is not idle.
5	M_ACTIVITY	R	0x0	Master Activity Status. When the Master is not in the IDLE state, this bit is set. Note: STAT[0], ACTIVITY bit, is the OR of S_ACTIVITY and M_ACTIVITY Y bits. Value: 0x0 (INACTIVE): Master is idle. 0x1 (ACTIVE): Master not idle.
4	RX_FIFO_CF	R	0x0	Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. Value: 0x0 (NOT_FULL): RX FIFO is not full. 0x1 (FULL): RX FIFO is full.
3	RX_FIFO_NE	R	0x0	Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. Value: 0x0 (EMPTY): RX FIFO is empty. 0x1 (NOT_EMPTY): RX FIFO not empty.
2	TX_FIFO_CE	R	0x1	Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. Value: 0x0 (NOT_EMPTY): TX FIFO not empty. 0x1 (EMPTY): TX FIFO is empty.
1	TX_FIFO_NF	R	0x1	Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. Value: 0x0 (FULL): TX FIFO is full. 0x1 (NOT_FULL): TX FIFO not full.
0	ACTIVITY	R	0x0	I2C Activity Status Value: 0x0 (INACTIVE): I2C is idle. 0x1 (ACTIVE): I2C is active.

TX_FIFO_LV

Name: I2C Transmit FIFO Level Register
Description: This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever:
- The I2C is disabled.
- If RAW_TX_ABORT bit is set in the RAW_INT_STAT register, the slave bulk transmit mode is aborted.
- The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
Base Address: 0x4000C300 + x*0x100
Offset: 0x74
Reset Value: 0x00000000

表 283 I2C Transmit FIFO Level Register
Bits	Field Name	RW	Reset	Description
31:4	RSVD	R		Reserved bits
3:0	TLEVEL	R	0x0	Transmit FIFO Level. It contains the number of valid data entries in the transmit FIFO.

RX_FIFO_LV

Name: I2C Receive FIFO Level Register
Description: This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever:
- The I2C is disabled.
- There is a transmit abort caused by any of the events tracked in TX_ABORT_SRC.
- The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.
Base Address: 0x4000C300 + x*0x100
Offset: 0x78
Reset Value: 0x00000000

表 284 I2C Receive FIFO Level Register
Bits	Field Name	RW	Reset	Description
31:4	RSVD	R		Reserved bits
3:0	LEVEL	R	0x0	Receive FIFO Level. It contains the number of valid data entries in the receive FIFO.

SDA_HOLD

Name: I2C SDA Hold Time Length Register
Description: I2C SDA Hold Time Length Register
- The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).
- The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.
- Writes to this register succeed only when EN[0]=0.
- The values in this register are in units of clock period. The value programmed in TX_HOLD must be greater than the minimum hold time in each mode one cycle in master mode, seven cycles in slave mode for the value to be implemented.
- The programmed SDA hold time during transmit (TX_HOLD) cannot exceed at any time the duration of the low part of SCL. Therefore the programmed value cannot be larger than N_SCL_LOW minus 2, where N_SCL_LOW is the duration of the low part of the SCL period measured in clock cycles.
Base Address: 0x4000C300 + x*0x100
Offset: 0x7C
Reset Value: 0x00000001

表 285 I2C SDA Hold Time Length Register
Bits	Field Name	RW	Reset	Description
31:24	RSVD	R		Reserved bits
23:16	RX_HOLD	RW	0x0	Set the required SDA hold time in units of clock period, when I2C acts as a receiver.
15:0	TX_HOLD	RW	0x1	Set the required SDA hold time in units of clock period, when I2C acts as a transmitter.

TX_ABORT_SRC

Name: I2C Transmit Abort Source Register
Description: I2C Transmit Abort Source Register
- This register has 32 bits that indicate the source of the TX_ABORT bit. Except for Bit 9, this register is cleared whenever the CLR_TX_ABORT register bit or the CLR_INT register is read. To clear Bit 9, the source of ABORT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (CTRL[5] = 1), the SPECIAL bit must be cleared (TARGET_ADDR[11]), or the TX_CTRL bit must be cleared (TARGET_ADDR[10]).
- Once the source of the ABORT_SBYTE_NORSTRT is fixed, this bit can be cleared in the same manner as other bits in this register. If the source of the ABORT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.
Base Address: 0x4000C300 + x*0x100
Offset: 0x80
Reset Value: 0x00000000

表 286 I2C Transmit Abort Source Register
Bits	Field Name	RW	Reset	Description
31:23	TX_FLUSH_CNT	R	0x0	This field indicates the number of TX FIFO Data Commands which are flushed due to TX_ABORT interrupt. It is cleared whenever I2C is disabled. Role of I2C: Master-Transmitter or Slave-Transmitter
22:18	RSVD	R		Reserved bits
17	ABRT_SDA_STUCK_AT_LOW	R	0x0	This is a master-mode-only bit. Master detects the SDA Stuck at low for the SDA_STUCK_AT_LOW_TIMEOUT value of ic_clk cycles. Value: 0x1 (ACTIVE): This abort is generated because of SDA stuck at low for SDA_STUCK_AT_LOW_TIMEOUT value of ic_clk cycles. 0x0 (INACTIVE): This abort is not generated.
16	ABORT_USER_ABORT	R	0x0	This is a master-mode-only bit. Master has detected the transfer abort (EN[1]) event. Role of I2C: Master-Transmitter Value: 0x0 (ABORT_USER_ABORT_VOID): Transfer abort not detected by master 0x1 (ABORT_USER_ABORT_GENERATED): Transfer abort detected by master
15	ABORT_SLVRD_INTX	R	0x0	When the processor side responds to a slave mode request for data to be transmitted to a remote master and users write a 1 in CMD (bit 8) of DATA_CMD register. Role of I2C: Slave-Transmitter Value: 0x0 (ABORT_SLVRD_INTX_VOID): Slave trying to transmit to remote master in read mode- scenario not present 0x1 (ABORT_SLVRD_INTX_GENERATED): Slave trying to transmit to remote master in read mode
14	ABORT_S_ARBLOST	R	0x0	This field indicates that a Slave has lost the bus while transmitting data to a remote master. TX_ABORT_SRC[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then I2C no longer owns the bus. Role of I2C: Slave-Transmitter Value: 0x0 (ABORT_S_ARBLOST_VOID): Slave lost arbitration to remote master- scenario not present 0x1 (ABORT_S_ARBLOST_GENERATED): Slave lost arbitration to remote master
13	ABORT_SLVFLUSH_TXFIFO	R	0x0	This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABORT interrupt to flush old data in TX FIFO. Role of I2C: Slave-Transmitter Value: 0x0 (ABORT_SLVFLUSH_TXFIFO_VOID): Slave flushes existing data in TX-FIFO upon getting read command- scenario not present 0x1 (ABORT_SLVFLUSH_TXFIFO_GENERATED): Slave flushes existing data in TX-FIFO upon getting read command
12	ABORT_LOST	R	0x0	This field specifies that the Master has lost arbitration, or if TX_ABORT_SRC[14] is also set, then the slave transmitter has lost arbitration. Role of I2C: Master-Transmitter or Slave-Transmitter Value: 0x0 (ABORT_LOST_VOID): Master or Slave-Transmitter lost arbitration- scenario not present 0x1 (ABORT_LOST_GENERATED): Master or Slave-Transmitter lost arbitration
11	ABORT_MASTER_DIS	R	0x0	This field indicates that users try to initiate a Master operation with the Master mode disabled. Role of I2C: Master-Transmitter or Master-Receiver Value: 0x0 (ABORT_MASTER_DIS_VOID): Users initiates master operation when Master is disabled- scenario not present 0x1 (ABORT_MASTER_DIS_GENERATED): Users initiates master operation when Master is disabled
10	ABORT_10B_RD_NORSTR	R	0x0	This field indicates that the restart is disabled (RESTART_EN bit (CTRL[5]) =0) and the master sends a read command in 10-bit addressing mode. Role of I2C: Master-Receiver Value: 0x0 (ABRT_10B_RD_VOID): Master not trying to read in 10-bit addressing mode when RESTART disabled 0x1 (ABRT_10B_RD_GENERATED): Master trying to read in 10-bit addressing mode when RESTART disabled
9	ABORT_SBYTE_NORSTRT	R	0x0	To clear Bit 9, the source of the ABORT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (RESTART_EN bit CTRL[5]=1), the SPECIAL bit must be cleared (TARGET_ADDR[11]), or the TX_CTRL bit must be cleared (TARGET_ADDR[10]). Once the source of the ABORT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABORT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, RESTART is disabled (RESTART_EN bit (CTRL[5]) =0) and users are trying to send a START BYTE. Role of I2C: Master Value: 0x0 (ABORT_SBYTE_NORSTRT_VOID): Users trying to send START BYTE when RESTART is disabled- scenario not present 0x1 (ABORT_SBYTE_NORSTRT_GENERATED): Users trying to send START BYTE when RESTART is disabled
8	ABORT_HS_NORSTRT	R	0x0	This field indicates that the RESTART is disabled (RESTART_EN bit (CTRL[5]) =0) and users are trying to use the master to transfer data in High-speed mode. Role of I2C: Master-Transmitter or Master-Receiver Value: 0x0 (ABORT_HS_NORSTRT_VOID): Users trying to switch Master to High-speed mode when RESTART is disabled- scenario not present 0x1 (ABORT_HS_NORSTRT_GENERATED): Users trying to switch Master to High-speed mode when RESTART is disabled
7	ABORT_SBYTE_ACKDET	R	0x0	This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Role of I2C: Master Value: 0x0 (ABORT_SBYTE_ACKDET_VOID): ACK detected for START byte- scenario not present 0x1 (ABORT_SBYTE_ACKDET_GENERATED): ACK detected for START byte
6	ABORT_HS_ACKDET	R	0x0	This field indicates that the Master is in High-speed mode and the High-speed Master code was acknowledged (wrong behavior). Role of I2C: Master Value: 0x0 (ABRT_HS_ACK_VOID): HS Master code ACKed in High-speed Mode- scenario not present 0x1 (ABRT_HS_ACK_GENERATED): High-speed Master code ACKed in High-speed Mode
5	ABORT_GCALL_RD	R	0x0	This field indicates that I2C in the master mode has sent a General Call but users program the byte that follows the General Call to be a read from the bus (DATA_CMD[9] is set to 1). Role of I2C: Master-Transmitter Value: 0x0 (ABORT_GCALL_RD_VOID): GCALL is followed by read from bus-scenario not present 0x1 (ABORT_GCALL_RD_GENERATED): GCALL is followed by read from bus
4	ABORT_GCALL_NOACK	R	0x0	This field indicates that I2C in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Role of I2C: Master-Transmitter Value: 0x0 (ABORT_GCALL_NOACK_VOID): GCALL not ACKed by any slave-scenario not present 0x1 (ABORT_GCALL_NOACK_GENERATED): GCALL not ACKed by any slave
3	ABORT_TX_NOACK	R	0x0	This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Role of I2C: Master-Transmitter Value: 0x0 (ABORT_TX_NOACK_VOID): Transmitted data non-ACKed by addressed slave-scenario not present 0x1 (ABORT_TX_NOACK_GENERATED): Transmitted data not ACKed by addressed slave
2	ABORT_10B2_NOACK	R	0x0	This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver Value: 0x0 (INACTIVE): This abort is not generated. 0x1 (ACTIVE): Byte 2 of 10-bit Address is not ACKed by any slave.
1	ABORT_10B1_NOACK	R	0x0	This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver Value: 0x0 (INACTIVE): This abort is not generated. 0x1 (ACTIVE): Byte 1 of 10-bit Address is not ACKed by any slave.
0	ABORT_7B_NOACK	R	0x0	This field indicates that the Master is in 7-bit address mode and the address sent was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver Value: 0x0 (INACTIVE): This abort is not generated. 0x1 (ACTIVE): This abort is generated because of NACK for 7-bit address.

DMA_CTRL

Name: DMA Control Register
Description: This register is only valid when I2C is configured with a set of DMA Controller interface signals. When I2C is not configured for DMA operation, this register does not exist and writing to the register address has no effect and reading from this register address will return zero. The register is used to enable the DMA Controller interface operation. There is a separate bit for transmitting and receiving. This can be programmed regardless of the state of EN.
Base Address: 0x4000C300 + x*0x100
Offset: 0x88
Reset Value: 0x00000000

表 287 DMA Control Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R		Reserved bits
1	TX_EN	RW	0x0	Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Value: 0x0 (DISABLED): Transmit FIFO DMA channel disabled 0x1 (ENABLED): Transmit FIFO DMA channel enabled
0	RX_EN	RW	0x0	Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Value: 0x0 (DISABLED): Receive FIFO DMA channel disabled 0x1 (ENABLED): Receive FIFO DMA channel enabled

DMA_TX_LV

Name: DMA Transmit Data Level Register
Description: This register is only valid when the I2C is configured with a set of DMA interface signals. When I2C is not configured for DMA operation, this register does not exist; writing to its address has no effect; reading from its address returns zero.
Base Address: 0x4000C300 + x*0x100
Offset: 0x8C
Reset Value: 0x00000000

表 288 DMA Transmit Data Level Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2:0	LEVEL	RW	0x0	Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic.

DMA_RX_LV

Name: DMA Receive Data Level Register
Description: This register is only valid when I2C is configured with a set of DMA interface signals. When I2C is not configured for DMA operation, this register does not exist; writing to its address has no effect; reading from its address returns zero.
Base Address: 0x4000C300 + x*0x100
Offset: 0x90
Reset Value: 0x00000000

表 289 DMA Receive Data Level Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2:0	LEVEL	RW	0x0	Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic.

SDA_SETUP

Name: I2C SDA Setup Register
Description: This register controls the amount of time delay (in terms of number of clock periods) introduced in the rising edge of SCL – relative to SDA changing – when I2C services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU_STO as detailed in the 图 57. This register must be programmed with a value that is equal to or greater than 2.

Writes to this register succeed only when EN[0] = 0.

Note:

The length of setup time is calculated using [(SDA_SETUP – 1)*(clk_period)], so if users require 10 clock periods of setup time, they should program a value of 11. The SDA_SETUP register is only used by the I2C when operating as a slave transmitter.

Base Address: 0x4000C300 + x*0x100
Offset: 0x94
Reset Value: 0x00000064

表 290 I2C SDA Setup Register
Bits	Field Name	RW	Reset	Description
31:8	RSVD	R		Reserved bits
7:0	SETUP	RW	0x64	SDA Setup. It is recommended that if the required delay is 1000 ns, then for a clock frequency of 10 MHz, SETUP should be programmed to a value of 11. SETUP must be programmed with a minimum value of 2.

ACK_GEN_CALL

Name: I2C ACK General Call Register
Description: The register controls whether I2C responds with an ACK or NACK when it receives an I2C General Call address. This register is applicable only when the I2C is in slave mode.
Base Address: 0x4000C300 + x*0x100
Offset: 0x98
Reset Value: 0x00000001

表 291 I2C ACK General Call Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	ACK_GEN_CALL	RW	0x1	ACK General Call. When this bit is set to 1, I2C responds with an ACK (by asserting data_oe) when it receives a General Call. Otherwise, I2C responds with a NACK (by negating data_oe). Value: 0x0 (DISABLED): Generate NACK for General Call. 0x1 (ENABLED): Generate ACK for a General Call.

EN_STAT

Name: I2C Enable Status Register
Description: The register is used to report the I2C hardware status when the EN[0] register bit is set from 1 to 0 (when I2C is disabled).
- If EN[0] has been set to 1, Bits [2:1] of the EN_STAT register are forced to 0, and Bit 0 is forced to 1.
- If EN[0] has been set to 0, Bits [2:1] of the EN_STAT register are only valid as soon as Bit 0 is read as '0'.

Note:

When EN[0] has been set to 0, a delay occurs for Bit 0 to be read as 0 because disabling the I2C depends on I2C bus activities.

Base Address: 0x4000C300 + x*0x100
Offset: 0x9C
Reset Value: 0x00000000

表 292 I2C Enable Status Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2	S_RX_DATA_LOST	R	0x0	Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of EN from 1 to 0. When this bit is read as 1, I2C is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK transfer, and EN[0] has been set to 0, then this bit is also set to 1. When this bit is read as 0, I2C is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. The CPU can safely read this bit when EN (bit 0) is read as 0. Value: 0x0 (INACTIVE): Slave RX Data is not lost 0x1 (ACTIVE): Slave RX Data is lost
1	S_DIS_BUSY	R	0x0	Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the EN register from 1 to 0. This bit is set when the CPU writes a 0 to the EN register while: I2C is receiving the address byte of the Slave-Transmitter operation from a remote master. Address and data bytes of the Slave-Receiver operation from a remote master. When this bit is read as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C (S_ADDR register) or if the transfer is completed before EN is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK a transfer, and EN[0] has been set to 0, then this bit will also be set to 1. When this bit is read as 0, I2C is deemed to have been disabled when there is master activity, or when the I2C bus is idle. The CPU can safely read this bit when EN (bit 0) is read as 0. Value: 0x0 (INACTIVE): Slave is disabled when it is idle 0x1 (ACTIVE): Slave is disabled when it is active
0	EN	R	0x0	EN Status. This bit always reflects the value driven on the output port EN. When read as 1, I2C is deemed to be in an enabled state. When read as 0, I2C is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read S_RX_DATA_LOST (bit 2) and S_DIS_BUSY (bit 1). Value: 0x0 (DISABLED): I2C disabled 0x1 (ENABLED): I2C enabled

FS_SPKLEN

Name: I2C SS, FS or FM+ Spike Suppression Limit
Description: This register is used to store the duration, measured in clock cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in Standard Mode (SS), Fast Mode (FS), or Fast Plus (FM+) Mode. The relevant I2C requirement is tSP as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.
Base Address: 0x4000C300 + x*0x100
Offset: 0xA0
Reset Value: 0x00000005

表 293 I2C SS, FS or FM+ spike suppression limit
Bits	Field Name	RW	Reset	Description
31:8	RSVD	R		Reserved bits
7:0	FS_SPKLEN	RW	0x5	This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in clock cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than 1 being written, and any attempt to write a value less than 1 results in 1 being set.

HS_SPKLEN

Name: I2C HS Spike Suppression Limit Register
Description: This register is used to store the duration, measured in clock cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in High-speed mode. The relevant I2C requirement is tSP as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1 and is implemented only if the component is configured to support High-speed mode.
Base Address: 0x4000C300 + x*0x100
Offset: 0xA4
Reset Value: 0x00000001

表 294 I2C HS Spike Suppression Limit Register
Bits	Field Name	RW	Reset	Description
31:8	RSVD	R		Reserved bits
7:0	HS_SPKLEN	RW	0x1	This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in clock cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than 1 being written, and any attempt to write a value less than 1 results in 1 being set.

SCL_STUCK_AT_LOW_TIMEOUT

Name: I2C SCL Stuck at Low Timeout Register
Description: This register is used to store the duration, measured in ic_clk cycles, used to generate an interrupt (SCL_STUCK_AT_LOW) if SCL is held low for the SCL_STUCK_LOW_TIMEOUT duration
Base Address: 0x4000C300 + x*0x100
Offset: 0xAC
Reset Value: 0xFFFFFFFF

表 295 I2C SCL Stuck at Low Timeout Register
Bits	Field Name	RW	Reset	Description
31:0	SCL_STUCK_LOW_TIMEOUT	RW	0xFFFFFFFF	I2C generates the interrupt to indicate SCL stuck at low (SCL_STUCK_AT_LOW) if it detects that the SCL is stuck at low for the SCL_STUCK_LOW_TIMEOUT in units of ic_clk period. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect.

SDA_STUCK_AT_LOW_TIMEOUT

Name: I2C SDA Stuck at Low Timeout Register
Description: This register is used to store the duration, measured in ic_clk cycles, used to recover the data (SDA) line through sending SCL pulses if SDA is held low for the SDA_STUCK_LOW_TIMEOUT duration
Base Address: 0x4000C300 + x*0x100
Offset: 0xB0
Reset Value: 0xFFFFFFFF

表 296 I2C SDA Stuck at Low Timeout Register
Bits	Field Name	RW	Reset	Description
31:0	SDA_STUCK_LOW_TIMEOUT	RW	0xFFFFFFFF	I2C initiates the recovery of SDA line through enabling the SDA_STUCK_RECOVERY_ENABLE (EN[3]) register bit, if it detects that the SDA is stuck at low for the SDA_STUCK_LOW_TIMEOUT in units of ic_clk period.

CLR_SCL_STUCK_DET

Name: Clear SCL Stuck at Low Detect Interrupt Register
Description: Clear SCL Stuck at Low Detect Interrupt Register
Base Address: 0x4000C300 + x*0x100
Offset: 0xB4
Reset Value: 0x00000001

表 297 I2C Clear SCL Stuck at Low Detect Interrupt Register
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	CLR_SCL_STUCK_DET	R	0x0	Read this register to clear the SCL_STUCK_AT_LOW interrupt (Bit 14) of the RAW_INT_STAT register.

Electrical Specifications

表 298 Electrical Specifications
Symbol	Parameter	Standard Mode (SS)		Fast Mode (FS)		Fast-plus Mode (FM+)		High-speed Mode (HS)		Unit
Symbol	Parameter	Min.	Max.	Min.	Max.	Min.	Max.	Min.	Max.	Unit
f_SCL	SCL clock frequency	0	100	0	400	0	1000	0	2000	kHz
t_L_OW	SCL clock LOW time	4.7	-	1.3	-	0.5	-	0.16	-	μs
t_HIGH	SCL clock HIGH time	4.0	-	0.6	-	0.26	-	0.06	-	μs
t_RSDA	SDArise time	-	1000	20	300	-	120	10	80	ns
t_FSDA	SDA fall time	-	300		300		120	10	80	ns
t_RSCL	SCLrise time	-	1000	20	300	-	120	10	40	ns
t_FSCL	SCL fall time	-	300		300		120	10	40	ns
t_{HD_STA}	START hold time	4.0	-	0.6	-	0.26	-	0.16	-	μs
t_{SU_DAT}	SDA setup time	250	-	100	-	50	-	10	-	ns
t_{HD_DAT}	SDA hold time	0	-	-	-	-	-	0	70	μs
t_{SU_STO}	STOP setup time	4.0	-	0.6	-	0.26	-	0.16	-	μs
t_BUF	BUS FREE time from STOP to START	4.7	-	1.3	-	0.5	-	-	-	μs

Note:

The bus load capacitance Cb = 100 pF.

I2C

Introduction

Main Features

Functional Description

I2C Operation

START and STOP Conditions

Addressing Slave

Transmitting and Receiving

SDA Hold Time

Registers

CTRL

TARGET_ADDR

S_ADDR

M_HS_ADDR

DATA_CMD

SS_CLK_HCNT

SS_CLK_LCNT

FS_CLK_HCNT

FS_CLK_LCNT

HS_CLK_HCNT

HS_CLK_LCNT

INT_STAT

INT_MASK

RAW_INT_STAT

RX_FIFO_THD

TX_FIFO_THD

CLR_INT

CLR_RX_UNDER

CLR_RX_OVER

CLR_TX_OVER

CLR_RD_REQ

CLR_TX_ABORT

CLR_RX_DONE

CLR_ACTIVITY

CLR_STOP_DET

CLR_START_DET

CLR_GEN_CALL

EN

STAT

TX_FIFO_LV

RX_FIFO_LV

SDA_HOLD

TX_ABORT_SRC

DMA_CTRL

DMA_TX_LV

DMA_RX_LV

SDA_SETUP

ACK_GEN_CALL

EN_STAT

FS_SPKLEN

HS_SPKLEN

SCL_STUCK_AT_LOW_TIMEOUT

SDA_STUCK_AT_LOW_TIMEOUT

CLR_SCL_STUCK_DET

Electrical Specifications

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