PWM

There are several shadow registers in the PWM module. The write operation will first change the shadow registers, and then will update the value of active registers from the shadow registers under certain conditions.

Active registers update conditions:

1. In synchronize-all update mode (UPDATE_SYNC_AE = 0x1), all effective registers of flicker mode or breath mode will be updated simultaneously. In flicker mode (BREATH_EN = 0), after writing to PRD, CMPxx and AQ_CTRL will update from shadow registers simultaneously when the Time Base counter counts to a value of PRD minus 1.

   

   In breath mode (BREATH_EN = 1), after writing to PRD, BR_PRD, and HOLD will update from shadow registers simultaneously when the current breath process ends (the moment PWM duty reduces to 0%). When using the app_pwm_update_freq interface, the PWM frequency will be updated immediately.

   

2. In synchronize-separate update mode (UPDATE_SYNC_AE = 0x0), PRD, CMPxx, and AQ_CTRL will update when the Time Base counter counts to value of the PRD register minus 1 if the corresponding UPDATE_SYNC_Sxx bit is set. BR_PRD and HOLD will update when the current breath process ends and the corresponding UPDATE_SYNC_Sxx bit is set.

3. In asynchronous update mode (UPDATE_SYNC_AE = 0x0 && UPDATE_SYNC_Sxx = 0x0), all registers will update instantly.

In initial state, set the update mode first, then PRD, CMPxx, AQ_CTRL, BR_PRD, and HOLD registers are configured, and then, drive mode is configured to choose the positive-drive mode or negative-drive mode, finally, choose breath mode or flicker mode and enable PWM.

The PWM duty cycle can be configured as an integer from 0 to 100, depending on the following calculation formulas of the duty cycle accuracy "n".

• In PWM_ALIGNED_EDGE mode:
  $$n=f_{\mathrm{PWM}}÷f_{\mathrm{SYSCLK}}\times 100$$

• In PWM_CENTER_EDGE mode:
  $$n=f_{\mathrm{PWM}}÷f_{\mathrm{SYSCLK}}\times 200$$

For example, when the clock frequency is 64 MHz, and the duty cycle is in the range of 0 to 100, the maximum PWM frequency can only be set to 640 kHz in the PWM_ALIGNED_EDGE mode and 320 kHz in the PWM_ALIGNED_CENTER mode.

In breath mode, in order to satisfy that the duty cycle of the waveform changes from 0 to 100 and then from 100 to 0, it is allowed to set the values of PRD and BR_PRD to an integer that is multiple(s) of 128. The freq, bperiod and hperiod in the structure pwm_init_t need to meet the following formula during initialization:

where, k represents the number of PWM cycles required for the duty cycle from 0% to 100%; SYS_CLK represents the system clock frequency.

• Name: Mode Register
• Description: This register sets the PWM operation mode.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x0
• Reset Value: 0x00000000

• Name: Update Register
• Description: This register is used to set the synchronous update mode.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x4
• Reset Value: 0x00000000

• Name: Period Register
• Description: This register is used to set the PWM cycle.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x8
• Reset Value: 0x64

• Name: Compare A0 Register
• Description: This register controls the PWM duty of Compare register 0 of channel A.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0xC
• Reset Value: 0x00000000

• Name: Compare A1 Register
• Description: This register controls the PWM duty of Compare register 1 of channel A.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x10
• Reset Value: 0x00000000

• Name: Compare B0 Register
• Description: This register controls the PWM duty of Compare register 0 of channel B.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x14
• Reset Value: 0x00000000

• Name: Compare B1 Register
• Description: This register controls the PWM duty of Compare register 1 of channel B.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x18
• Reset Value: 0x00000000

• Name: Compare C0 Register
• Description: This register controls the PWM duty of Compare register 0 of channel C.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x1C
• Reset Value: 0x00000000

• Name: Compare C1 Register
• Description: This register controls the PWM duty of Compare register 1 of channel C.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x20
• Reset Value: 0x00000000

• Name: Action Qualifier Control Register
• Description: This register is used to set actions when counter reaches the compare value.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x24
• Reset Value: 0x00000000

• Name: Breath Period Register
• Description: This register configures the period of breath mode.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x28
• Reset Value: 0x00000000

• Name: Hold Register
• Description: This register configures the hold period in breath mode.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x2C
• Reset Value: 0x00000000