Comparator

The following figure shows the overview of the wakeup comparator module.

The Vbatl_ref comes from Vbatl through resistor divided, as shown in the 图 147. Once enabled by using the COMP_REG_0.COMP_EN register, the comparator starts to work. When the wakeup comparator module is started, V1 starts to be compared with V2 continuously. When V1 exceeds V2, the wakeup interrupt will be triggered. The COMP_REG_0.CHANNEL_SEL_P_3_0 and COMP_REG_0.CHANNEL_SEL_N_3_0 registers are used to select the input of V1 and V2. When Vbatl_ref is selected in the COMP_REG_0.CHANNEL_SEL_N_3_0 or COMP_REG_0.CHANNEL_SEL_P_3_0 register, the bit COMP_REG_1.EN_VBATL_REF should be enabled first. The COMP_REG_0.COMP_VBATL_LVL_CTRL_2_0 register is used to select a level value of Vbatl_ref. The COMP_VBATL_LVL_CTRL_2_0 level value ranges from 0 to 7, and the calculation formula of Vbatl_ref is shown below:

When Vref is selected in the COMP_REG_0.CHANNEL_SEL_P_3_0 or COMP_REG_0.CHANNEL_SEL_N_3_0 register, the bit COMP_REG_1.EN_REF should be enabled first. The COMP_REG_0.COMP_REF_CTRL_7_0 register is used to select a level value of Vref. The COMP_REF_CTRL_7_0 level value ranges from 0 to 255 and can be configured by COMP_REG_0.COMP_REF_CTRL_7_0 register. The calculation formula of Vref is shown below. Iref comes from the relatively constant current generated by the chip's bandgap module and will not be affected by other modules, as shown in the 图 148.

The selected analog pins will be acquired by the comparator once it is enabled.

The configurable 52 mV (±26 mV) hysteresis could be added into the wakeup comparator, which helps ensure the slowly changing voltage or a slightly noisy voltage that will cause the comparator not to output to oscillate frequently when the two input voltages are almost close. This could increase the anti-interference ability of the comparator. The hysteresis mode can be configured in COMP_REG_1.HYS_EN. The hysteresis on both sides mode is illustrated in 图 149. The comparator will trigger a falling edge interrupt whenever V1 becomes lower than V2- (VHYST/2). It will also trigger a rising edge interrupt whenever V1 becomes higher than V2+ (VHYST/2). Here it is assumed that V1 is connected to the positive side of the comparator, and V2 is connected to the negative side of the comparator.

The clock source for collecting the comp output signal is shown in the figure below. The clock can be set as 250 kHz or 2 MHz by configuring the aon_slow_clk_sel. A higher clock frequency will improve the sampling accuracy, but correspondingly increase the power consumption.

Res degeneration is set for calibration. The default values of COMP_REG_1.RDEG_N_3_0 register and COMP_REG_1.RDEG_P_3_0 register are 0x8 and are always kept unchanged. The COMP module obtains positive and negative res degeneration which means users can calibrate the comparator by adjusting positive and negative sides. For example, when the comparator outputs a valid signal, the voltage values at N and P sides of the comparator should be approximately equal; if it is found that the actual voltage at P side is too much larger than that at N side, you can set the value of COMP_REG_1.RDEG_P_3_0 smaller, or set the value of COMP_REG_1.RDEG_N_3_0 larger.

The COMP_REG_1.CASCRES_HALF register is used to ensure that the comparator is in proper operation at different bias currents.

• The COMP_REG_1.CASCRES_HALF is set to 1 for half resistor when COMP_REG_0.ICOMP_CTRL_3_0 is close to 0000.
• The COMP_REG_1.CASCRES_HALF is set to 0 for full resistor when COMP_REG_0.ICOMP_CTRL_3_0 is close to 1111.

The COMP_REG_0. ICOMP_CTRL_3_0 register is used to configure the bias current. Higher bias currents will reduce the response time of the comparator, but with a corresponding increase in power consumption. Lower bias currents will increase the response time of the comparator, but with a corresponding reduce in power consumption. It is worth noting that this bias current is also from bandgap module, but this current and Iref are independent of each other and will not interfere with each other.

Glitch Remove

When the voltage reaches the threshold, the signal from the comp output will jitter because of noise interference. In order to eliminate jitter, users can specify a time by configuring the PMU_COMP_GLITCH_REMOVE.GLITCH_REMOVE_CYCLE register and the signal is considered valid if it does not change within this period of time. As the following figure shows, if the duration of the signal is less than the user set time Glitch_t, then the probability of triggering the interrupt will be greatly reduced. If the duration of the signal is larger than the user set time Glitch_t, then the interrupt will definitely be triggered.

• Name: Comparator Register 0
• Description: This register includes REF_VALUE setting, COMP enablement, and channel selection.
• Base Address: 0x4000A800
• Offset: 0x40
• Reset Value: 0x00000000

表 745 Comparator Register 0

Bits	Field Name	RW	Reset	Description
23:20	CHANNEL_SEL_N_3_0	WR	0x0	Wakeup comparator channel N selection: 0–7: MSIO_0–MSIO_7 8: GND 9: Vbatl_ref 10: Vref
19:16	CHANNEL_SEL_P_3_0	WR	0x0	Wakeup comparator channel P selection: 0–7: MSIO_0–MSIO_7 8: GND 9: Vbatl_ref 10: Vref
15:8	COMP_REF_CTRL_7_0	WR	0x0	COMP REF CTRL (Vref) Changes the BG-based reference: Min = 0 V, Max =1.9 V (step = 7.5 mV). 11111111: 1.9 V 00000000: 0 V
7	COMP_EN	WR	0x0	Enables or disables wakeup comparator. 0: Disable 1: Enable
6:4	COMP_BATT_LVL_CTRL_2_0	WR	0x0	Changes the Vbatl based ref (Vbatl_vref): 000: Vbatl/10 001: 2 Vbatl/10 … 111 :8 Vbatl/10
3:0	ICOMP_CTRL_3_0	WR	0x0	0000: Max current (1 μA) 1111: Min current (50 nA)

• Name: Comparator Register 1
• Description: This register includes res degeneration, reference source enable, CascRes Half, and Hysteresis.
• Base Address: 0x4000A800
• Offset: 0x44
• Reset Value: 0x00000088

表 746 Comparator Register 1

Bits	Field Name	RW	Reset	Description
15	EN_REF	WR	0x0	1: Enable internal Vref. 0: Disable internal Vref.
14	EN_VBATL_REF	WR	0x0	1: Enable Vbatl_ref. 0: Disable Vbatl_ref.
13	CASCRES_HALF	WR	0x0	CascRes Half: 1: Half resistor (high power when ICOMP_CTRL_3_0 is close to 0000) 0: Full resistor (low power when ICOMP_CTRL_3_0 is close to 1111)
12:10	RSVD	R	0x0	Reserved bits
9:8	HYS_EN	WR	0x0	00: No hysteresis 01: Positive Hysteresis only 10: Negative Hysteresis only 11: Hysteresis on both sides Hysteresis = 26 mV
7:4	RDEG_N_3_0	WR	0x8	Res degeneration N, for calibration only
3:0	RDEG_P_3_0	WR	0x8	Res degeneration P, for calibration only

• Name: MCU Wakeup Control Register of COMP
• Description: For each bit, 0 indicates IRQ is disabled, and 1 indicates IRQ is enabled.
• Base Address: 0x4000A000
• Offset: 0x80
• Reset Value: 0x0000FFFF

表 747 MCU Wakeup Control Register of COMP

Bits	Field Name	RW	Reset	Description
11	EVT_PMU_MSIO_COMP_F	WR	0X1	1: Enable the wakeup function of the comp falling edge. 0: Disable the wakeup function of the comp falling edge.
5	EVT_PMU_MSIO_COMP	WR	0x1	1: Enable the wakeup function of the comp rising edge. 0: Disable the wakeup function of the comp rising edge.

• Name: AON Sleep Event Register of COMP
• Description: Events that happen in sleep or active mode, controlled by MCU_WKUP_CTRL.

• Base Address: 0x4000A000
• Offset: 0x84
• Reset Value: 0x00000000

表 748 AON Sleep Event Register of COMP

Bits	Field Name	RW	Reset	Description
11	EVT_PMU_MSIO_COMP_F	WR	0x0	Write 0 to this bit to clear comp falling event.
5	EVT_PMU_MSIO_COMP	WR	0x0	Write 0 to this bit to clear rising comp event.

• Name: COMP Glitch Remove Register
• Description: To remove voltage jitter, add deglitch circuit on comparator output (glitch: from 4 μs to 28 μs at a 4 μs step).
• Base Address: 0x4000A000
• Offset: 0x2C0
• Reset Value: 0x00000000

表 749 COMP Glitch Remove Register

Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2:0	GLITCH_REMOVE_CYCLE	WR	0	0: No glitch removal 1–7: 4 μs*N glitch removal