Flash (Non-Volatile Memory)
The non-volatile memory management system integrates an accessible Flash memory, on-chip QSPI controller, and XIP controller – all allow GR5526 SoCs to be capable of storing application data and code execution in Flash address.
The XIP mechanism allows the CPU to execute program code directly from the internal Flash memory by using the QSPI interface. When a cache miss occurs, the XIP controller will automatically prefetch a certain number of program instructions from Flash memory and update them into the cache memory.
Write and Erase
Flash memory can be read by the CPU unlimited times through the XIP controller, but the number of times it can be written or erased (up to 100000 cycles) and how it can be written are restricted.
Writing to Flash memory is managed by the on-chip QSPI controller. Before performing a write/erase, the XIP controller must be disabled for writing and the on-chip QSPI controller must be enabled. After writing/erasing, software needs to restore the XIP controller. Users must make sure that writing and erasing are not performed at the same time. If the CPU executes code from Flash while the on-chip QSPI controller is writing to Flash, the CPU execution will be stalled. In this case, the SRAM should be used for code execution.
The Flash memory is only able to write ‘0’ to erased bits, but it cannot write a bit back to ‘1’. Therefore, a page action must be performed before a write to the same address in Flash. GR5526 supports write operations both in encryption mode and non-encryption mode. The data written in encryption mode is protected from being read arbitrarily. In encryption mode, Flash is written by a full 32-bit word to a word-aligned address in Flash. At the same time, write and erase operations of the Flash are 4 KB as a loop to respond to external interrupts, so as to avoid operations occupying CPU for a long time and causing the external process being crowded.
After a Flash page is erased, all bits in the page are set to ‘1’. The time required for erasing is determined by the electrical parameters of the Flash, as shown in 表 16. The CPU is stalled if the CPU executes code from the Flash while the controller performs erase operations.
Flash Operation Interfaces
All the Flash operation interfaces have been provided by the GR5526 SDK package to ensure security of Flash operations. Users do not need to care about the implementation details of Flash operations.
Electrical Specifications
| Description | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|
|
Erase Suspend Latency |
30 |
μs |
||
|
Program Suspend Latency |
30 |
μs |
||
|
Latency between Program Resume and next Suspend |
0.3 |
μs |
||
|
Latency between Erase Resume and next Suspend |
0.3 |
μs |
||
|
Page Program time (up to 256 bytes) |
8 |
20 |
ms |
|
|
Sector Erase time |
8 |
20 |
ms |
|
|
Chip Erase time |
8 |
20 |
ms |
|
| Program/Erase Cycles | 100000 | cycles |
If the data length (Ldata_length, 4-byte aligned) in each Flash Program is longer or equal to 40 bytes, the Flash max Erase cycle is 100000; if the Program data length is less than 40 bytes, you can calculate the max Erase cycle base on the formula:
For example, if the data length in each Flash Program is 4, then the max Erase cycle is 10000. If your product Flash Erase cycle is higher than the result from the formula, you can add data cache to reduce the Flash Program times or trade more Flash space for Flash Program times.
