PWM

In flicker mode, the PWM module outputs successive pulses with a certain frequency and duty as configured. PRD register is used to configure the frequency in the flicker mode. The duty of PWM can be configured in the range of 0% to 100% through CMPx0, CMPx1 and AQCTRL register. The three outputs can be configured independently, and they share one output frequency.

In flicker mode, if the stop level is configured (the default value of FLICKER_PAUSE_LEVEL_x is 0 when not set), the I/O level of the corresponding channel will be pulled to the set value when PWM stops.

In breath mode, the duty of PWM output periodically changes from 0% to 100%, and then 100% to 0% uniformly. The breathing cycle can be set by the BRPRD register, which represents the number of PWM cycles required for the duty cycle 0%→100% and then 100%→0%.

A configurable duration of breath hold state (can be set by the HOLD rgister) is supported. The breath hold state is set between two adjacent breath processes, that is duty change (0%→100%→0%), breath hold, and duty change (0%→100%→0%). In the hold state, the PWM output is driven by inactive state.

In breath mode, the I/O levels of all channels are the same and set by the BREATH_PAUSE_LEVEL bit in the MODE register when PWM stops. When MCU enters sleep state, the stop level remains high in both flicker mode and breath mode.

In flicker mode, both edge alignment and center alignment are supported through software approach.

• Choose edge alignment mode, as shown in Figure 39. All open channels are aligned at the beginning of each duty cycle.

  

• Choose center alignment mode, as shown in Figure 40. All open channels are aligned in the middle of each duty cycle.

  

PWM module is capable of configuring output frequency dynamically. There are several shadow registers in the PWM module. The write operation will first change the shadow registers, and then will update the value of active registers from the shadow registers under certain conditions.

The configured data can be updated into active registers in three modes: synchronize-all mode (enabled by UPDATE.SA), synchronize-separate mode (enabled by UPDATE.SSCMPxx) and asynchronous update mode (enabled by UPDATE.SA and UPDATE.SSCMPxx).

Active registers update conditions:

1. In synchronize-all update mode (UPDATE.SA = 0x1), all effective registers of flicker mode or breath mode will be updated simultaneously. In flicker mode (MODE.BREATHEN = 0), after writing to PRD, the CMPxx and AQCTRL registers will update from shadow registers simultaneously when the Time Base counter counts to a value of PRD minus 1.

   In breath mode (MODE.BREATHEN = 1), after writing to PRD, the BRPRD and HOLD registers will update from shadow registers simultaneously when the current breath process ends (the moment PWM duty reduces to 0%). When using the app_pwm_update_freq interface, the PWM frequency will be updated immediately.

2. In synchronize-separate update mode (UPDATE.SA = 0x0), the PRD, CMPxx, and AQCTRL registers will update when the Time Base counter counts to value of the PRD register minus 1, and if the corresponding UPDATE.SSCMPxx bit is set. The BRPRD and HOLD registers will update when the current breath process ends and the corresponding UPDATE.SSCMPxx bit is set.

3. In asynchronous update mode (UPDATE.SA = 0x0 and UPDATE.SSCMPxx = 0x0), all registers will update instantly.

   If the configurations need to be changed under synchronize-all update mode, CMPXX and AQCTRL in flicker mode, or HOLD in breath mode should be written before modifying the values of PRD and BRPRD.

The PWM duty cycle can be configured as an integer from 0 to 100, depending on the following calculation formulas of the duty cycle accuracy "n".

• In edge-aligned mode:
  
  

  

  
  

• In center-aligned mode:
  
  

  

  
  

For example, when the clock frequency is 64 MHz, and the duty cycle is in the range of 0 to 100, the maximum PWM frequency can only be set to 640 kHz in the edge-aligned mode and 320 kHz in the center-aligned mode.

In breath mode, in order to satisfy that the duty cycle of the waveform changes from 0 to 100 and then from 100 to 0, it is necessary to set the values of PRD and BRPRD to an integer that is multiple(s) of 128. The freq, bperiod and hperiod in the structure pwm_init_t need to meet the following formula during initialization:

where, k represents the number of PWM cycles required for the duty cycle from 0% to 100%; SYS_CLK represents the system clock frequency; bperiod represents the breath period; hperiod represents the hold period.

• Name: Mode Register
• Description: This register sets the PWM operation mode.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x0
• Reset Value: 0x00000000

• Name: Update Register
• Description: This register is used to set the synchronous update mode.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x4
• Reset Value: 0x00000000

• Name: Period Register
• Description: This register is used to set the PWM cycle.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x8
• Reset Value: 0x00000064

• Name: Compare A0 Register
• Description: This register controls the PWM duty of Compare register 0 of channel A.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0xC
• Reset Value: 0x00000000

• Name: Compare A1 Register
• Description: This register controls the PWM duty of Compare register 1 of channel A.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x10
• Reset Value: 0x00000000

• Name: Compare B0 Register
• Description: This register controls the PWM duty of Compare register 0 of channel B.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x14
• Reset Value: 0x00000000

• Name: Compare B1 Register
• Description: This register controls the PWM duty of Compare register 1 of channel B.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x18
• Reset Value: 0x00000000

• Name: Compare C0 Register
• Description: This register controls the PWM duty of Compare register 0 of channel C.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x1C
• Reset Value: 0x00000000

• Name: Compare C1 Register
• Description: This register controls the PWM duty of Compare register 1 of channel C.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x20
• Reset Value: 0x00000000

• Name: Action Qualifier Control Register
• Description: This register is used to set actions when counter reaches the compare value.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x24
• Reset Value: 0x00000000

• Name: Breath Period Register
• Description: This register configures the period of breath mode.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x28
• Reset Value: 0x00000000

• Name: Hold Register
• Description: This register configures the hold period in breath mode.
• Base Address: 0x4000CB00 + x*0x100
• Offset: 0x2C
• Reset Value: 0x00000000