Reset Reason Recorder
In the SoC, a reset reason recorder module is implemented in the always-on domain. When a reset is triggered, a specific flag register is set by hardware. The flag register is accumulative, which means it hold the status until a software clear is applied. The reset recorder will be helpful in debug when the system is reset accidentally.
Reset Reason Status
The reset reason status can be obtained through the DBG_REG_RST_SRC register. As shown in 图 34, POR reset or watchdog reset will cause Power State Controller to reset, thus resulting in an active mcu_core_rst_n reset to the SoC. Using the digital logic software reset will record as system full reset in the reset reason recorder. When the digital logic power changes in POR reset, system full reset, AON Watchdog reset and sleep reset, the sleep reset will be recorded in the reset reason recorder.
| Item | DBG_REG_RST_SRC [5:0] | |||||
|---|---|---|---|---|---|---|
| Reset reson | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 |
| POR reset | 1 | 1 | 0 | 0 | 0 | 0 |
| System full reset | 1 | 0 | 1 | 0 | 0 | 0 |
| AON Watchdog reset | 1 | 0 | 0 | 1 | 0 | 0 |
| Sleep reset | 1 | 0 | 0 | 0 | 0 | 0 |
|
System reset (SYSRESETREQ) |
0 | 0 | 0 | 0 | 0 | 1 |
Programming
When the DBG_REG_RST_SRC register is used to clear flags, the following applies:
- Write 1 to bit[0]–bit[5] of the DBG_REG_RST_SRC register to clear the corresponding reset flag.
When the DBG_REG_RST_SRC register is used to enable reset recording, the following applies:
- Writing 1 to both bit[24] and bit[31] of the DBG_REG_RST_SRC register starts an enabling process.
- As clock domain crossing takes about 2-3 256k clocks time, perform polling on bit[16] of the DBG_REG_RST_SRC register until the Reset Reason Recorder block is ready (high).
