System Buses
The device contains a set of AMBA buses which move data between peripherals, memory, and the Arm® Cortex®-M4F processor.
The Arm® Cortex®-M4F processor provides generic bus interfaces based on Advanced Microcontroller Bus Architecture (AMBA). The AMBA specification supports several bus protocols for communication between memories and peripherals. The main bus interface uses the AHB Lite protocol.
- I-Code bus interface: Primarily for program memory; fetches instructions from the ‘Code’ memory space (0x0 to 0x1FFFFFFF).
- D-Code bus interface: Primarily for program memory; supports data and debug accesses to the ‘Code’ memory space (0x0 to 0x1FFFFFFF).
- System bus interface: Primarily for RAM and peripherals; accesses the SRAM and other peripherals of the MCU.
Among them, I-CODE and D-CODE are independent from the system bus. They can realize parallel data access and value acquisition, which can effectively improve performance. The MCU maps the available SRAM onto an address space within the ‘Code’ memory space. This gives the application the opportunity to perform tasks efficiently because the system can quickly finish the task and go to sleep mode.
The infrequently accessed peripherals of the MCU are located on an AMBA advanced peripheral bus (APB). There is a bridge which translates accesses from the System AHB to the advanced high-performance bus (APB). Access to these peripherals will inject a single wait-state on the AHB during any access cycle.
In addition, it provides better performance in data access and higher flexibility. The AHB matrix ports support DMA and CPU access to different memories and peripherals at the same time. When multiple masters access the same memory or peripheral concurrently, the SoC supports setting the access priorities of the masters based on round-robin scheduling according to the access sequence, instead of using a fixed priority. After each response to the master request, the priority will be determined.
AHB Connection Matrix
The following figure shows the AHB matrix, which is a 7-master-10-slave bus matrix based on AMBA AHB multi-layer. The blue boxes on the top represent the modules that act as AHB masters, whereas the orange ones on the right are AHB slaves. The solid triangles on the crossing lines indicate accessible paths between masters and slaves.
In total, seven bus masters are implemented:
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MST0: D-Code bus of Cortex®-M4F CPU core
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MST1: I-Code bus of Cortex®-M4F CPU core
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MST2: System bus of Cortex®-M4F CPU core
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MST3: DMA AHB master
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MST4: Hopping table master for AM mode. It fetches address and data from a memory bank for parameter register.
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MST5: Bluetooth LE MAC master that is responsible for data exchange between memory banks and the communication core.
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MST6: Modem ferp master is similar to Bluetooth LE MAC master. It can be used when Bluetooth LE MAC is bypassed.
AHB Multilayer Arbitration
The round robin method is used when multiple masters access the same slave at the same time, during which each master connected to the multi-layer AHB is assigned a default natural priority based on its slave interface (SI) number. Specifically, the master with a lower SI number is given higher priority than a master with a higher SI number. The masters and their SI numbers are shown in 表 11. When more than one master device initiates access to the same slave device simultaneously, the master device with the lowest SI number is granted access first, whereas other bus master devices with higher SI numbers need to wait until the higher-priority master device has completed its transaction.
Based on AHB protocol, AHB multilayer allows parallel access paths between multiple masters and slaves in a system. AHB multilayer provides a bus layer for each bus master, with each layer connected to one slave through a slave multiplexer, reducing latencies while increasing the bus bandwidth available to multi-master systems. The bus masters are assigned with priorities to help the SoC in granting access when two (or more) bus masters concurrently request access to the same slave device. In the process, the following rules apply:
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If two (or more) bus masters concurrently request access to the same slave device, the master with the highest priority is granted the access first.
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Bus masters with lower priorities need to wait until the higher-priority master has completed its transaction.
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If the higher-priority master pauses at any point during its transaction, the next lower priority master in queue is temporarily granted access to the slave device until the higher priority master resumes its activity.
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Bus masters that share the same priority are mutually exclusive, thus cannot be used concurrently.
However, some peripherals lack a safe stalling mechanism, which means they are unable to stop incoming data. As a result, being a low priority master might cause a loss of data for such peripherals upon bus contention. To avoid AHB contention when multiple bus masters are used, apply one of the following guidelines:
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Avoid situations where more than one bus master accesses the same slave.
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If it cannot be avoided, make sure that the bus bandwidth is not exhausted before masters access the slave.
Each master connected to the AHB multilayer is assigned a default priority, indicated by the SI number, as provided in the table below.
| Bus Master Name | SI Number | In/Out |
|---|---|---|
CPU D-Code |
SI0 |
I/O |
CPU I-Code |
SI1 |
I/O |
CPU System Bus |
SI2 |
I/O |
DMA |
SI3 |
I/O |
Htable |
SI4 |
O |
BLE MAC |
SI5 |
I/O |
Modem Ferp |
SI6 |
I/O |
Bus Faults
The bus will receive a bus fault when:
- The core attempts to access an address that is illegal, which means the host access crosses address boundaries.
- The slave sends a transmission error message to the host with an ERROR response.
In addition, the bus fault interrupt can be enabled or disabled when any transfer error occurs on the bus.
