High Frequency Clocks

HFXO_32M is a crystal-based oscillator that connects to a 32 MHz external crystal. The startup time of HFXO_32M depends on the crystal type as well as the internal bias current. The bias current is programmable to reduce the power consumption when the HFXO_32M clock settles.

HFXO_32M is used in application scenarios that require high precision and temperature sensitivity, such as Bluetooth RF. During the processing of Bluetooth tasks, HFXO_32M should be turned on. The SoC can use xo16m_clk, which is generated by dividing HFXO_32M by two, as the system clock at the initial stage of power-on. After normal booting, it is able to switch to user-configured system clock.

• Used to drive 32 MHz crystals
• Programmable on-chip capacitor array for frequency calibration
• Programmable bias current to optimize different crystals, supporting a wide range of equivalent series resistance (ESR) and equivalent series inductance (ESL)
• Fast setup mode disabled, can be enabled on demand
• Mapping divided HFXO_2M to pin

The prerequisite for HFXO_32M to be turned on is to wait for the DC-DC converter or SYS_LDO to be powered on.

When the system meets the following conditions, the HFXO_32M will be turned on.

• When the system meets one of the following conditions during the wakeup period, the hardware will automatically turn on HFXO_32M.
  • HFXO_32M is enabled when AON_START_CFG.XO_EN_PWR = 0x1.
  • CPLL_192M is enabled when AON_START_CFG.PLL_EN_PWR = 0x1.
  • HFXO_32M is selected as the system clock when MCU_CLK_CTRL.MCU_CLK_CTRL_SEL = 0x2.
  • CPLL_192M is selected as the system root working clock when AON_CLK.CAL_FST_CLK = 0x0.
• If one of the following registers is configured, HFXO_32M is forced to be turned on at any time.
  • MCU_CLK_CTRL.MCU_CLK_CTRL_SEL = 0x2
  • AON_CLK.CAL_FST_CLK = 0x0
• If XO_PLL_SET.XO_SET= 1, HFXO_32M will be requested to be turned on.
• If the behavior of enabling CPLL_192M occurs, HFXO_32M will also be turned on.
• If COMM_CORE_PWR_CTRL_HW_CFG.PLL_AUTO_ON = 1, both HFXO_32M and CPLL_192M will be automatically turned on when the Bluetooth LE Timer interrupt is triggered.

When the system meets the one of following conditions, the HFXO_32M will be turned off.

• Before the system enters sleep mode, both DC-DC converter and SYS_LDO are disabled when A_SLP_CFG.TRN_OFF_DCDC = 1 and A_SLP_CFG.TRN_OFF_FAST_LDO = 1
• Auto HFXO_32M off function during sleep is enabled when A_SLP_CFG.TRN_OFF_XO = 1
• If the bit XO_PLL_CLR.XO_CLR is set to 1, HFXO_32M will be requested to be turned off.

By default, the system uses hardware to control signals. In order to improve the flexibility, the SoC provides overriding registers to allow software to control signals. The state of HFXO_32M can be configured by the overriding registers.

• Set status to the RF_INTF_OVR_VAL_0.XO_EN bit.
• Enable override function by setting the RF_INTF_OVR_EN_0.XO_EN bit to 1.
• The status of HFXO_32M can be obtained by reading from the RF_INTF_OVR_RD_0.XO_EN bit.

When HFXO_32M is running in steady operation state, it is possible to trim the frequency by modifying the tuning capacitance through the RF9[18:10] bits. Ideally, changing the RF9[18:10] bits by one LSB at one time will modify the frequency of the HFXO_32M. Sufficient time should elapse to wait for the HFXO_32M to stabilize before making frequency measurement.

The bias current of the HFXO_32M affects the power consumption. The bias current can be adjusted through the RF_XO_BIAS_VAL register after the DC-DC converter or SYS_LDO power on.

• When requesting to turn on HFXO_32M, the bias current of the HFXO_32M can be reduced by configuring the RF_XO_BIAS_VAL.BIAS_LO register.
• When requesting to turn off HFXO_32M, the bias current of the HFXO_32M can be increased by configuring the RF_XO_BIAS_VAL.BIAS_HI register.

Due to the deviation of the chip process, the most suitable bias current configuration needs to be obtained through actual test.

The SoC supports mapping the HFXO_2M from the HFXO_32M on pin. For detailed description of the mapping, refer to "Clock Mapping on Pin".

表 58 HFXO_32M crystal oscillator specifications

Parameter	Symbol	Min.	Typ.	Max.	Unit
HFXO_32M frequency	HFXO_32MFREQ		32		MHz
Accuracy	HFXO_32MACC			100	ppm
Equivalent series resistance	HFXO_32MESR			80	Ω
Load capacitance	HFXO_32MLCAP	6		8	pF
Startup time (without su)	HFXO_32MSTIM			1000	μs
Startup time (with su)	HFXO_32MSTIMSU			500	μs

CPLL_192M is obtained by multiplying the HFXO_32M clock source by the phase-locked loop (CPLL) circuit. The multiplied clock is used to generate the main system clock for the RF and digital sections.

CPLL_192M is also used to tune frequency hopping to obtain the desired value for each packet. The settling time of CPLL_192M is designed to be within the time defined by the Bluetooth LE specifications to maintain the interframe space (IFS) timing.

• Frequency locked at 192 MHz
• Low output jitter
• Lock detection module with flag bit
• Mapping divided clock to pin

The prerequisite for CPLL_192M to be turned on is to wait for HFXO_32M to be stable. When the system meets the following conditions, the CPLL_192M will be turned on.

• When the system meets one of the following conditions during the wakeup period, the CPLL_192M will be turned on.
  • CPLL_192M is enabled when AON_START_CFG.PLL_EN_PWR = 0x1
  • CPLL_192M is enabled when AON_CLK.CAL_FST_CLK = 0x0
• If the AON_CLK.CAL_FST_CLK bit is set to 0, CPLL_192M will be forced to be turned on at any time.
• If the COMM_CORE_PWR_CTRL_HW_CFG.PLL_AUTO_ON bit is set to 1, CPLL_192M will be automatically turned on when the Bluetooth LE Timer interrupt is triggered.
• If the XO_PLL_SET.PLL_SET register is set to 1, CPLL_192M will be requested to be turned on.

When the system meets one of the following conditions, the CPLL_192M will be turned off.

• If the HFXO_32M is turned off, the CPLL_192M is turned off due to the loss of reference clock source.
• Auto CPLL_192M off function during sleep is enabled when A_SLP_CFG.TRN_OFF_PLL = 1
• If the XO_PLL_CLR.PLL_CLR bit is set to 1, CPLL_192M will be requested to be turned off..

By default, the system uses hardware to control signals. In order to improve the flexibility, the SoC provides overriding registers to allow software to control signals. The current state of CPLL_192M can be controlled by the overriding registers.

• Set status to the RF_INTF_OVR_VAL_0.CPLL_EN bit and the RF_INTF_OVR_VAL_0.RST_N bit.
• Enable override function by setting RF_INTF_OVR_EN_0.CPLL_EN = 1 and RF_INTF_OVR_EN_0.RST_N = 1.
• The status of CPLL_192M can be obtained by reading from the RF_INTF_OVR_RD_0.CPLL_EN bit and RF_INTF_OVR_RD_0.RST_N bit.

The CPLL circuit is able to output other frequency by configuring the RF6 and RF7 registers. However, the SoC usually only use the 192MHz frequency in application so that the CPLL will be locked at 192 MHz.

表 59 CPLL_192M oscillator specifications

Parameter	Symbol	Min.	Typ.	Max.	Unit
Output frequency	CPLL_192MFREQ		192		MHz
Deviation across temperature	CPLL_192MACC	-500		500	ppm/°C

The high-frequency RC oscillator (HFRC_192M) is an internal 192 MHz clock used for fast system startup, providing system clock for MCU. HFRC_192M will be turned on during the initial stage of power-on by default. Due to the individual differences of the RC oscillators, the frequency of each HFRC_192M might vary on SoCs.

Due to the accuracy and temperature sensitivity, the high-frequency RC oscillator (HFRC_192M) is required to switch to HFXO_32M clock if a Bluetooth LE connection is established. In applications where no high-precision clock is required, the high-frequency RC oscillator (HFRC_192M) can replace CPLL_192M in order to reduce the power consumption.

• 192 MHz high frequency RC oscillator
• Low frequency-temperature coefficient with automatic adapt
• Low current consumption
• Fast startup
• Online calibration
• Mapping divided clock to a pin

When the system meets one of the following conditions, the HFRC_192M will be turned on.

• System needs to wait for DC-DC converter or SYS_LDO to complete power-on before HFRC_192M can be turned on during the wakeup period.
• If the XO_PLL_SET.HF_OSC_SET bit is set to 1, HFRC_192M will be requested to be turned on.

When the system meets the one of the following conditions, the HFRC_192M will be turned off.

• Auto HFRC_192M off function during sleep is enabled when A_SLP_CFG.TRN_OFF_HF_OSC = 1
• On the premise that the system clock does not use HFRC_192M, the HFRC_192M can be turned off through the XO_PLL_CLR.HF_OSC_CLR bit.

By default, the system uses hardware to control signals. In order to improve the flexibility, the SoC provides overriding registers to allow software to control signals. The current state of HFRC_192M can be controlled by the overriding registers.

• Set status to the PMU_INTF_OVR_VAL_0.HF_OSC_EN bit.
• Enable override function by setting the PMU_INTF_OVR_EN_0.HF_OSC_EN bit to 1.
• The status of HFRC_192M can be obtained by reading from the PMU_INTF_OVR_RD0.HF_OSC_EN bit.

Since the actual frequency of HFRC_192M will be variable due to process deviation, it is able to adjust the frequency through the FS_REG_0 and FS_REG_1 registers.

• FS_REG_0.FINE_CODE allows fine adjustment of the frequency of HFRC_192M.
• FS_REG_1[3:0] allows coarse adjustment of the frequency of HFRC_192M.

Normally, the operation step is to adjust the frequency of HFRC_192M to the specified range through the coarse adjustment register first, and then adjust the frequency of the HFRC_192M through the fine adjustment register.

The SoC supports online calibration of the HFRC_192M through high precision crystal oscillator. For detailed description of the calibration, refer to "Clock Calibration".

表 60 HFRC_192M oscillator specifications

Parameter	Symbol	Min.	Typ.	Max.	Unit
Output frequency	HFRC_192MFREQ	183.3	192	196	MHz
Deviation across temperature	HFRC_192MACC	–500	265	500	ppm/°C