Hardware Reset
External Reset Pin
The active-low CHIP_EN pin can be used to generate a POR reset by using an off-chip component. There is no internal pull-up resistor on this pin. The CHIP_EN pin is not maskable. The up voltage of the CHIP_EN pin is 1.4 V, and the down voltage of the CHIP_EN pin is 0.8 V.
Watchdog Reset
A watchdog timer (WDT) reset is generated when the watchdog timer times out. The watchdog is on by default, and its time-out count value is 200,000 clock cycles of “aon_timer_clock”, roughly 6 seconds by default. The software will re-perform cold boot after watchdog reset.
For detailed description of the watchdog timer, refer to "Always-on Watchdog (AON_WDT)".
