Functional description

GR551x only support DMA as flow controller. There are four transfer types as follow:

• Memory to memory
• Memory to peripheral
• Peripheral to memory
• Peripheral to peripheral

For memory, source transfer width must be less than or equal to AHB master interface data bus width, normally 8, 16 or 32 bits. For a non-memory, source transfer width is equal to the peripheral FIFO Width.

For memory, destination transfer width must be less than or equal to AHB master interface data bus width, normally 8, 16 or 32 bits. For a non-memory, destination transfer width is equal to the peripheral FIFO Width.

• Source address increment: indicates whether to increase or decrease the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change.
• Destination address increment: whether to increment or decrement the destination address on every source transfer. If the device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No change.

Each channel has a programmable priority in range 0 – 7, lowest to highest. Channel priority work for most scenario except in master bus. It is worth noting that a request for the master bus interface can be made at any time, but is granted only after the current AHB transfer (burst or single) is completed. Therefore, when the master interface is transferring data for a low priority channel while a high priority channel requests service, it completes the current AHB transfer (burst or single) for the low priority channel before switching to transfer data for the high one.

DMA has 8 channels and each channel has a 32-bit FIFO. The 8 FIFOs are independent of each other. After the DMA channel is enabled, the DMA obtains data from the source according to the bit width configured for the source port, stores the data into the DMA FIFO, takes out the data from the DMA FIFO according to the bit width configured for the destination port, and sends the data to the destination port. Regardless of the configured transmission bit width, the data obtained from the source is compactly stored, which can also maximize the use of DMA FIFO storage space. For example, the transmission bit width is 16-bit wide and the FIFO bit width is 32-bit wide, so that one depth of DMA FIFO will store two pieces of 16-bit wide data. When DMA is used as flow control, the total size of data in bytes (blk_size_bytes_dma) transmitted by DMA in a single transmission is equal to the product of the source transmission bit width (src_single_size_bytes) and the block size (BLOCK_XFE_SIZE).