Registers

RTC_CTRL

表 29 RTC_CTRL
Bits	Field Name	RW	Reset	Description
31:14	RSVD	R		Reserved bits
13	WRAP_INT_EN	RW	0x1	Wrap-around interrupt enable. Value: 0x0: Disable 0x1: Enable
12	ALARM_INT_EN	RW	0x1	Timer alarm interrupt enable. Value: 0x0: Disable 0x1: Enable
11	RSVD	R		Reserved bits
10:8	CLK_SEL	RW	0x1	Timer clock select. Refer to 表 27.
7:4	WRAP_CNT	R	0x0	Wrap-around counter
3	RSVD	R		Reserved bits
2	ALARM_VAL_LOAD	W	0x0	Alarm value load. Write 1 to load the value.
1	VAL_LOAD	W	0x0	Up counter value load. Write 1 to load the value.
0	EN	RW	0x0	Enable calendar timer. Value: 0x0: Disable 0x1: Enable

表 32 VAL_SET
Bits	Field Name	RW	Reset	Description
31:0	VAL_SET	RW	0x0	This register is shared with multiple timers. To apply the value, set the value then assert corresponding load registers.

表 33 VAL_RD
Bits	Field Name	RW	Reset	Description
31:0	VAL_RD	R	0x0	This register is to read the current value and shared with multiple timers.