Hardware Behavior

The SIM clock is derived from the module clock by dividing it by CLK_CFG.CLK_DIV.

The SIM clock frequency shall be in the range of 1 to 5 MHz, 4 MHz during UICC initialization and 5 MHz during normal operation. The clock division has to be chosen accordingly.

The UICC active low reset pin shall be driven by the SIM interface output, and RST controlled by the register CTRL.ACTION.

The bidirectional I/O pad on chip top level is implemented as open drain with a recommended pull up to VCC of 20 kΩ. If supported by the UICC the I/O pad can use low impedance drivers to save power.

UICC card holder often serve a card presence contact. Any card presence change will trigger an interrupt (see STAT.PRESENCE_STAT and STAT.IRQ_PRESENCE).

The activation sequence and cold reset sequence is shown in 图 52. At first VCC is ramped up. With T_a the clock starts while the reset is still asserted. On T_b the reset is released and the UICC has to start with the ATR within t_c.

The I/O pin is not actively driven by the SIM interface during the entire cold reset procedure. The high level is ensured by the pull up resistor. Therefore t_a is not implemented in the SIM interface.

t_b is hard-coded to 400 clock cycles.

The minimum t_c is not checked by the SIM interface module.

The maximum t_c is defined by register fields CLK_CFG.ETU_DIV and TIMES_CFG.WAIT_TIME with respect to (6). The reset values are chosen according the specification to receive the ATR without any modifications. CLK_CFG.ETU_DIV is 371 and TIMES.WAITTIME is 107 (see (7)).

If maximum t_c is not met by the UICC, interrupt STAT.IRQ_RX_ERR is triggered.

The warm reset sequence is shown in 图 53.

The warm reset is implemented identical to the cold reset, with T_c = T_a, T_d =T_b, t_d =t_a, t_e = t_b and t_f =t_c.

Due to the fact that the registers CLK_CFG and TIMES_CFG may have changed after the ETU evaluation, the reset values have to be restored by firmware before triggering the warm reset.

The clock stop sequence is shown in 图 54.

The times t_g and t_h are ensured by the SIM interface hardware module, with and .

The UICC deactivation sequence is shown in 图 55.

The times t_i and t_j are ensured by the SIM interface hardware module, with and .

The timing t_k depends on the VCC source.

The nominal duration of one moment on the electrical circuit I/O is named Elementary Time Unit (ETU).

The ETU shall be equal to F/D clock cycles on the electrical circuit CLK where F and D are the transmission parameters. F is the clock rate conversion integer and D is the baud rate adjustment integer. F, D and f are negotiated during the initialization and setup by firmware. Possible values for F and D are shown in 表 249.

表 249 Values for F and D

F	D	F/D
372	1	372
372	2	186
372	3	124
372	4	93
512	1	512
512	2	256
512	4	128
512	8	64
512	16	32
512	32	16
512	64	8

f is configured as described in CLK.

The chosen ETU has to be written to register field CLK_CFG.ETU_DIV.

Fractional ETU times are not supported.

The character transmission timing is shown in 图 56. A character consists of:

• Start Bit
• 8 Data Bits
• Parity Bit
• 2 Stop Bits with error signaling

• RX

In case of detected parity error during reception, the behavior depends on register field STAT.RX_RETRY_MAX. If the number of retries is not exceeded, the I/O pin is pulled low for one clock cycle to trigger a retransmission. Otherwise or if RETRY_MAX = 0, the received byte is discarded and the reception is aborted with a STAT.IRQ_RETRY_ERR interrupt. The internal retry counter is restarted with every character.

The maximum number of retries during the reception of one byte is displayed in register field STAT.RX_RETRY_MAX and cleared via CTRL.RX_RETYR_MC.

• TX

In case of an error signaling from the receiver, the behavior depends on register field STAT.TX_RETRY_MAX. If the number of retries is not exceeded, the character is retransmitted. Otherwise or if RETRY_MAX = 0, the transmission is aborted with a STAT.IRQ_RETRY_ERR interrupt. The internal retry counter is restarted with every character.

The maximum number of retries during the transmission of one byte is displayed in register field STAT.TX_RETRY_MAX and cleared via CTRL.TX_RETYR_MC.

The guard time specifies the minimum time between the leading edge of two consecutive characters, which has to be taken into account by the transmitter. The wait time specifies the maximum time between the leading edge of two consecutive characters, which has to be monitored by the receiver before issuing a timeout.

The guard time is adjusted by register field TIMES_CFG.GUARD_TIME and respected before transmitting a character. This includes the scenario, when the SIM interface has received a character and starts a transmission afterwards. The minimal guard time is 12. Register field TIMES_CFG.GUARD_TIME values smaller than that are ignored.

The wait time is adjusted by register field TIMES_CFG.WAIT_TIME and respected before aborting a character reception.

The Byte DMA accesses memory addresses word-wise and interacts with the I/O module on a byte base. In transmitting process, one entire word is read and served byte-wise. Irrelevant bytes are simply ignored. In receiving process, the word is cleared at the beginning and filled byte-wise. After the 4th byte or after receiving the last byte, the entire word is written to the memory.

Receive and transmit buffer share the same start address (register START_ADDR), which has to be aligned to 4.

The internal word address counting is limited to 18 Bit. Therefore the maximum receive and transmit buffer sizes are limited to 2⁽¹⁸⁺²⁾ Bytes (1 MB). The buffer shall not cross a 1 MB address boundary.

The receive buffer end address is controlled by register RX_END_ADDR and has to be calculated according to (10) for an expected number of bytes N_RX.

A done interrupt will be issued after receiving N_RX bytes.

If less bytes are received and the wait time is expired, an rx_err interrupt is triggered. The register addr points to the last received byte, which can be used to calculate the number of received bytes n_rx.

If more bytes are served by the UICC than expected, an rx_err interrupt is triggered too, but the incoming bytes are ignored and addr stays untouched.

The transmit buffer end address is controlled by register TX_END_ADDR and has to be calculated according to (12) for an expected number of bytes NTX.

A DMA error interrupt dma_err is triggered under the following conditions:

• Invalid address
• Bus slave responses with an error
• Word could not be read within one ETU
• Word could not be written within one character