gr533x_ll_xqspi.h
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1 /**
2  ****************************************************************************************
3  *
4  * @file gr533x_ll_xqspi.h
5  * @author BLE SDK Team
6  * @brief Header file containing functions prototypes of XQSPI LL library.
7  *
8  ****************************************************************************************
9  * @attention
10  #####Copyright (c) 2019 GOODIX
11  All rights reserved.
12 
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14  modification, are permitted provided that the following conditions are met:
15  * Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17  * Redistributions in binary form must reproduce the above copyright
18  notice, this list of conditions and the following disclaimer in the
19  documentation and/or other materials provided with the distribution.
20  * Neither the name of GOODIX nor the names of its contributors may be used
21  to endorse or promote products derived from this software without
22  specific prior written permission.
23 
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34  POSSIBILITY OF SUCH DAMAGE.
35  ****************************************************************************************
36  */
37 
38 /** @addtogroup PERIPHERAL Peripheral Driver
39  * @{
40  */
41 
42 /** @addtogroup LL_DRIVER LL Driver
43  * @{
44  */
45 
46 /** @defgroup LL_XQSPI XQSPI
47  * @brief XQSPI LL module driver.
48  * @{
49  */
50 
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR533x_LL_XQSPI_H__
53 #define __GR533x_LL_XQSPI_H__
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 /* Includes ------------------------------------------------------------------*/
60 #include "gr533x.h"
61 
62 #if defined (XQSPI)
63 
64 /** @defgroup LL_XQSPI_DRIVER_STRUCTURES Structures
65  * @{
66  */
67 
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup XQSPI_LL_ES_INIT XQSPI Exported init structure
70  * @{
71  */
72 
73 /**
74  * @brief XQSPI High Performance mode init structures definition
75  */
76 typedef struct _ll_xqspi_hp_init_t
77 {
78  uint8_t xqspi_hp_enable; /**< Specifies If enable the HP mode for XQSPI.
79  This parameter can be a value of @ref XQSPI_HP_MODE_EN */
80 
81  uint8_t xqspi_hp_cmd; /**< Specifies the command to enter HP mode for XQSPI. */
82 
83  uint8_t xqspi_hp_end_dummy; /**< Specifies the end dummpy cycle in HP mode for XQSPI. */
84 
85 } ll_xqspi_hp_init_t;
86 /** @} */
87 
88 /**
89  * @brief XQSPI init structures definition
90  */
91 typedef struct _ll_xqspi_init_t
92 {
93  uint32_t mode; /**< Specifies the work mode, XIP mode or QSPI mode.
94  This parameter can be a value of @ref XQSPI_LL_EC_MODE.*/
95 
96  uint32_t cache_mode; /**< Specifies the cache mode in XIP mode.
97  This parameter can be a value of @ref XQSPI_LL_EC_CACHE_MODE.
98 
99  This feature can be modified afterwards using unitary function @ref ll_xqspi_enable_cache().*/
100 
101  uint32_t read_cmd; /**< Specifies the XQSPI read command in XIP mode.
102  This parameter can be a value of @ref XQSPI_LL_EC_XIP_READ_CMD.
103 
104  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cmd().*/
105 
106  uint32_t data_size; /**< Specifies the XQSPI data width, only in QSPI mode.
107  This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATASIZE.
108 
109  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_datasize().*/
110 
111  uint32_t data_order; /**< Specifies the XQSPI data order, MSB oe LSB, only in QSPI mode.
112  This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATAORDER.
113 
114  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_data_order().*/
115 
116  uint32_t clock_polarity; /**< Specifies the serial clock steady state.
117  This parameter can be a value of @ref XQSPI_LL_EC_QSPI_POLARITY in XIP mode or @ref XQSPI_LL_EC_QSPI_POLARITY in QSPI mode.
118 
119  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cpol() or @ref ll_xqspi_set_qspi_cpol().*/
120 
121  uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
122  This parameter can be a value of @ref XQSPI_LL_EC_QSPI_PHASE in XIP mode or @ref XQSPI_LL_EC_QSPI_PHASE in QSPI mode.
123 
124  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_xip_cpha() or @ref ll_xqspi_set_qspi_cpha().*/
125 
126  uint32_t baud_rate; /**< Specifies the BaudRate be used to configure the transmit and receive SCK clock.
127  This parameter can be a value of @ref XQSPI_LL_EC_QSPI_BAUD_REAT.
128 
129  This feature can be modified afterwards using unitary function @ref ll_xqspi_set_qspi_speed().*/
130 
131  uint32_t cache_direct_map_en; /**< Specifies the XQSPI Cache work on direct map or 4-way set associative.
132  This parameter can be a value of @ref XQSPI_LL_CACHE_DIRECT_MAP_EN.*/
133 
134  uint32_t cache_flush; /**< Specifies the XQSPI Cache will be flushed or not.
135  This parameter can be a value of @ref LL_XQSPI_CACHE_FLUSH_EN.*/
136 
137  ll_xqspi_hp_init_t hp_init; /**< Specifies the XQSPI HP mode Configuration.
138  This structures is defined @ref ll_xqspi_hp_init_t.*/
139 
140 } ll_xqspi_init_t;
141 
142 /** @} */
143 
144 /** @} */
145 
146 /**
147  * @defgroup XQSPI_LL_MACRO Defines
148  * @{
149  */
150 
151 /* Exported constants --------------------------------------------------------*/
152 /** @defgroup XQSPI_LL_Exported_Constants XQSPI Exported Constants
153  * @{
154  */
155 
156 /** @defgroup XQSPI_HP_MODE_EN XQSPI HP mode
157  * @{
158  */
159 #define LL_XQSPI_HP_MODE_DIS 0 /**< Disable XQSPI High Performance mode */
160 #define LL_XQSPI_HP_MODE_EN 1 /**< Enable XQSPI High Performance mode */
161 /** @} */
162 
163 /** @defgroup XQSPI_LL_EC_MODE XQSPI work mode
164  * @{
165  */
166 #define LL_XQSPI_MODE_XIP 0 /**< XIP mode */
167 #define LL_XQSPI_MODE_QSPI 1 /**< QSPI mode */
168 /** @} */
169 
170 /** @defgroup XQSPI_LL_EC_XIP_READ_CMD XIP read command
171  * @{
172  */
173 #define LL_XQSPI_XIP_CMD_READ 0x03 /**< Read mode */
174 #define LL_XQSPI_XIP_CMD_FAST_READ 0x0B /**< Fast Read mode */
175 #define LL_XQSPI_XIP_CMD_DUAL_OUT_READ 0x3B /**< Dual-Out Fast Read mode */
176 #define LL_XQSPI_XIP_CMD_DUAL_IO_READ 0xBB /**< Dual-IO Fast Read mode */
177 #define LL_XQSPI_XIP_CMD_QUAD_OUT_READ 0x6B /**< Quad-Out Fast Read mode */
178 #define LL_XQSPI_XIP_CMD_QUAD_IO_READ 0xEB /**< Quad-IO Fast Read mode */
179 /** @} */
180 
181 /** @defgroup XQSPI_LL_EC_XIP_SS Slave select
182  * @{
183  */
184 #define LL_XQSPI_XIP_SS0 (1UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 0 */
185 #define LL_XQSPI_XIP_SS1 (2UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 1 */
186 #define LL_XQSPI_XIP_SS2 (4UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 2 */
187 #define LL_XQSPI_XIP_SS3 (8UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 3 */
188 /** @} */
189 
190 /** @defgroup XQSPI_LL_EC_XIP_ADDR_MODE Address bytes in command
191  * @{
192  */
193 #define LL_XQSPI_XIP_ADDR_3BYTES 0x00000000UL /**< Address command is 3 bytes */
194 #define LL_XQSPI_XIP_ADDR_4BYTES XQSPI_XIP_CFG_ADDR4 /**< Address command is 4 bytes */
195 /** @} */
196 
197 /** @defgroup XQSPI_LL_EC_XIP_ENDIAN Read data endian mode
198  * @{
199  */
200 #define LL_XQSPI_XIP_ENDIAN_BIG 0x00000000UL /**< Read data in big endian */
201 #define LL_XQSPI_XIP_ENDIAN_LITTLE XQSPI_XIP_CFG_LE32 /**< Read data in little endian */
202 /** @} */
203 
204 /** @defgroup XQSPI_LL_EC_CACHE_MODE XIP cache mode
205  * @{
206  */
207 #define LL_XQSPI_CACHE_DIS 0 /**< Cache OFF */
208 #define LL_XQSPI_CACHE_EN 1 /**< Cache ON */
209 /** @} */
210 
211 /** @defgroup XQSPI_LL_EC_CACHE_FIFO_MODE Cache FIFO mode
212  * @{
213  */
214 #define LL_XQSPI_CACHE_FIFO_NORMAL 0x00000000UL /**< FIFO in normal mode */
215 #define LL_XQSPI_CACHE_FIFO_CLEAR XQSPI_CACHE_CTRL0_FIFO /**< FIFO in clear mode */
216 /** @} */
217 
218 /** @defgroup XQSPI_LL_EC_CACHE_HITMISS_COUNTER_MODE Cache hit/miss counters mode
219  * @{
220  */
221 #define LL_XQSPI_CACHE_HITMISS_NORMAL 0x00000000UL /**< Hit/Miss counters in normal mode */
222 #define LL_XQSPI_CACHE_HITMISS_CLEAR XQSPI_CACHE_CTRL0_HITMISS /**< Hit/Miss counters in clear mode */
223 /** @} */
224 
225 /** @defgroup XQSPI_LL_EC_QSPI_FLAG QSPI Flags Defines
226  * @brief Flags defines which can be used with LL_XQSPI_ReadReg function
227  * @{
228  */
229 #define LL_XQSPI_QSPI_STAT_RFTF XQSPI_QSPI_STAT_RXWMARK /**< Rx FIFO watermark flag */
230 #define LL_XQSPI_QSPI_STAT_RFF XQSPI_QSPI_STAT_RXFULL /**< Rx FIFO full flag */
231 #define LL_XQSPI_QSPI_STAT_RFE XQSPI_QSPI_STAT_RXEMPTY /**< Rx FIFO empty flag */
232 #define LL_XQSPI_QSPI_STAT_TFTF XQSPI_QSPI_STAT_TXWMARK /**< Tx FIFO watermark flag */
233 #define LL_XQSPI_QSPI_STAT_TFF XQSPI_QSPI_STAT_TXFULL /**< Tx FIFO full flag */
234 #define LL_XQSPI_QSPI_STAT_TFE XQSPI_QSPI_STAT_TXEMPTY /**< Tx FIFO empty flag */
235 #define LL_XQSPI_QSPI_STAT_BUSY XQSPI_QSPI_STAT_XFERIP /**< Busy flag */
236 /** @} */
237 
238 /** @defgroup XQSPI_LL_EC_QSPI_IT QSPI interrupt Defines
239  * @brief Interrupt defines which can be used with LL_XQSPI_ReadReg and LL_XQSPI_WriteReg functions
240  * @{
241  */
242 #define LL_XQSPI_QSPI_IM_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt enable */
243 #define LL_XQSPI_QSPI_IM_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt enable */
244 #define LL_XQSPI_QSPI_IM_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt enable */
245 #define LL_XQSPI_QSPI_IM_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt enable */
246 #define LL_XQSPI_QSPI_IM_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt enable */
247 
248 #define LL_XQSPI_QSPI_IS_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt flag */
249 #define LL_XQSPI_QSPI_IS_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt flag */
250 #define LL_XQSPI_QSPI_IS_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt flag */
251 #define LL_XQSPI_QSPI_IS_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt flag */
252 #define LL_XQSPI_QSPI_IS_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt flag */
253 /** @} */
254 
255 /** @defgroup XQSPI_LL_EC_QSPI_FIFO_WATERMARK QSPI FIFO Watermark
256  * @{
257  */
258 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_8 0UL /**< FIFO depth/8 */
259 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_4 1UL /**< FIFO depth/4 */
260 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_2 2UL /**< FIFO depth/2 */
261 #define LL_XQSPI_QSPI_FIFO_WATERMARK_3_4 3UL /**< FIFO depth*3/4 */
262 #define LL_XQSPI_QSPI_FIFO_DEPTH 8UL /**< FIFO full depth */
263 /** @} */
264 
265 /** @defgroup XQSPI_LL_EC_QSPI_FRAMEFORMAT QSPI Frame Format
266  * @{
267  */
268 #define LL_XQSPI_QSPI_FRF_SPI 0x00000000UL /**< SPI frame format for transfer */
269 #define LL_XQSPI_QSPI_FRF_DUALSPI (2UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Dual-SPI frame format for transfer */
270 #define LL_XQSPI_QSPI_FRF_QUADSPI (3UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Quad-SPI frame format for transfer */
271 /** @} */
272 
273 /** @defgroup XQSPI_LL_EC_QSPI_DATAORDER QSPI Data Order
274  * @{
275  */
276 #define LL_XQSPI_QSPI_LSB 0x00000000UL /**< LSB first for transfer */
277 #define LL_XQSPI_QSPI_MSB XQSPI_QSPI_CTRL_MSB1ST /**< MSB first for transfer */
278 /** @} */
279 
280 /** @defgroup XQSPI_LL_EC_QSPI_DATASIZE QSPI Datawidth
281  * @{
282  */
283 #define LL_XQSPI_QSPI_DATASIZE_4BIT 0x00000000UL /**< Data length for XQSPI transfer: 4 bits */
284 #define LL_XQSPI_QSPI_DATASIZE_8BIT (1UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 8 bits */
285 #define LL_XQSPI_QSPI_DATASIZE_12BIT (2UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 12 bits */
286 #define LL_XQSPI_QSPI_DATASIZE_16BIT (3UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 16 bits */
287 #define LL_XQSPI_QSPI_DATASIZE_20BIT (4UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 20 bits */
288 #define LL_XQSPI_QSPI_DATASIZE_24BIT (5UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 24 bits */
289 #define LL_XQSPI_QSPI_DATASIZE_28BIT (6UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 28 bits */
290 #define LL_XQSPI_QSPI_DATASIZE_32BIT (7UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI transfer: 32 bits */
291 /** @} */
292 
293 /** @defgroup XQSPI_LL_EC_QSPI_PHASE QSPI Clock Phase
294  * @{
295  */
296 #define LL_XQSPI_SCPHA_1EDGE 0 /**< First clock transition is the first data capture edge */
297 #define LL_XQSPI_SCPHA_2EDGE 1 /**< Second clock transition is the first data capture edge */
298 /** @} */
299 
300 /** @defgroup XQSPI_LL_EC_QSPI_POLARITY QSPI Clock Polarity
301  * @{
302  */
303 #define LL_XQSPI_SCPOL_LOW 0 /**< Clock to 0 when idle */
304 #define LL_XQSPI_SCPOL_HIGH 1 /**< Clock to 1 when idle */
305 /** @} */
306 
307 /** @defgroup XQSPI_LL_EC_QSPI_BAUD_REAT QSPI Buad Rate
308  * @{
309  */
310 #define LL_XQSPI_BAUD_RATE_64M 0x00000000UL /**< Clock to 64MHz */
311 #define LL_XQSPI_BAUD_RATE_48M (1UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos) /**< Clock to 48MHz */
312 #define LL_XQSPI_BAUD_RATE_32M (2UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos) /**< Clock to 32MHz */
313 #define LL_XQSPI_BAUD_RATE_24M (3UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos) /**< Clock to 24MHz */
314 #define LL_XQSPI_BAUD_RATE_16M (4UL << AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL_Pos) /**< Clock to 16MHz */
315 /** @} */
316 
317 /** @defgroup XQSPI_LL_CACHE_DIRECT_MAP_EN XQSPI Cache direct map enable
318  * @{
319  */
320 #define LL_XQSPI_CACHE_DIRECT_MAP_DIS 0 /**< Cache work on 4-Way Set Associative */
321 #define LL_XQSPI_CACHE_DIRECT_MAP_EN 1 /**< Cache work on Direct Map */
322 
323 /** @defgroup XQSPI_LL_CACHE_FLUSH_EN XQSPI Cache flush enable
324  * @{
325  */
326 #define LL_XQSPI_CACHE_FLUSH_DIS 1 /**< Cache Flush Disable */
327 #define LL_XQSPI_CACHE_FLUSH_EN 0 /**< Cache Flush Enable */
328 
329 /** @} */
330 
331 /** @defgroup XQSPI_LL_EC_QSPI_PRESENT QSPI Present Bypass
332  * @{
333  */
334 #define LL_XQSPI_ENABLE_PRESENT 0 /**< Enable Present Bypass */
335 #define LL_XQSPI_DISABLE_PRESENT 1 /**< Disable Present Bypass */
336 /** @} */
337 
338 /** @defgroup XQSPI_LL_EC_QSPI_FLASH_WRITE QSPI Flash write bits
339  * @{
340  */
341 #define LL_XQSPI_FLASH_WRITE_128BIT 0 /**< 128bits flash write */
342 #define LL_XQSPI_FLASH_WRITE_32BIT 1 /**< 32bits flash write */
343 /** @} */
344 
345 /** @defgroup XQSPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
346  * @{
347  */
348 
349 /**
350  * @brief LL XQSPI InitStrcut default configuartion
351  */
352 #define LL_XQSPI_DEFAULT_CONFIG \
353 { \
354  .mode = LL_XQSPI_MODE_QSPI, \
355  .cache_mode = LL_XQSPI_CACHE_EN, \
356  .read_cmd = LL_XQSPI_XIP_CMD_READ, \
357  .data_size = LL_XQSPI_QSPI_DATASIZE_8BIT, \
358  .data_order = LL_XQSPI_QSPI_MSB, \
359  .clock_polarity = LL_XQSPI_SCPOL_HIGH, \
360  .clock_phase = LL_XQSPI_SCPHA_2EDGE, \
361  .baud_rate = LL_XQSPI_BAUD_RATE_16M, \
362  .cache_direct_map_en= LL_XQSPI_CACHE_DIRECT_MAP_DIS, \
363  .cache_flush = LL_XQSPI_CACHE_FLUSH_EN, \
364 }
365 /** @} */
366 
367 /** @} */
368 
369 /* Exported macro ------------------------------------------------------------*/
370 /** @defgroup XQSPI_LL_Exported_Macros XQSPI Exported Macros
371  * @{
372  */
373 
374 /** @defgroup XQSPI_LL_EM_WRITE_READ Common Write and read registers Macros
375  * @{
376  */
377 
378 /**
379  * @brief Write a value in XQSPI register
380  * @param __instance__ XQSPI instance
381  * @param __REG__ Register to be written
382  * @param __VALUE__ Value to be written in the register
383  * @retval None
384  */
385 #define LL_XQSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
386 
387 /**
388  * @brief Read a value in XQSPI register
389  * @param __instance__ XQSPI instance
390  * @param __REG__ Register to be read
391  * @retval Register value
392  */
393 #define LL_XQSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
394 
395 /** @} */
396 
397 /** @} */
398 
399 /** @} */
400 
401 /* Exported functions --------------------------------------------------------*/
402 /** @defgroup XQSPI_LL_DRIVER_FUNCTIONS Functions
403  * @{
404  */
405 
406 /** @defgroup XQSPI_LL_XQSPI_Configuration Cache driver functions
407  * @{
408  */
409 
410 /**
411  * @brief Enable cache function
412  * @note This bit should not be changed when XIP is ongoing.
413  *
414  * Register|BitsName
415  * --------|--------
416  * CTRL0 |EN
417  *
418  * @param XQSPIx XQSPI instance
419  * @retval None
420  */
421 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
422 {
423  CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
424  __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
425 }
426 
427 /**
428  * @brief Disable cache function
429  * @note This bit should not be changed when XIP is ongoing.
430  *
431  * Register|BitsName
432  * --------|--------
433  * CTRL0 |EN
434  *
435  * @param XQSPIx XQSPI instance
436  * @retval None
437  */
438 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
439 {
440  SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
441  __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
442 }
443 
444 /**
445  * @brief Check if cache function is enabled
446  *
447  * Register|BitsName
448  * --------|--------
449  * CTRL0 |EN
450  *
451  * @param XQSPIx XQSPI instance
452  * @retval State of bit (1 or 0).
453  */
454 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
455 {
456  return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS) != (XQSPI_CACHE_CTRL0_DIS));
457 }
458 
459 /**
460  * @brief Enable cache direct map function
461  * @note This bit should not be changed when XIP is ongoing.
462  *
463  * Register|BitsName
464  * --------|--------
465  * CTRL0 |DIRECT_MAP
466  *
467  * @param XQSPIx XQSPI instance
468  * @retval None
469  */
470 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_cache_direct_map_enable(xqspi_regs_t *XQSPIx)
471 {
472  SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIRECT_MAP_EN);
473  __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
474 }
475 
476 /**
477  * @brief Disable cache direct map function
478  * @note This bit should not be changed when XIP is ongoing.
479  *
480  * Register|BitsName
481  * --------|--------
482  * CTRL0 |DIRECT_MAP
483  *
484  * @param XQSPIx XQSPI instance
485  * @retval None
486  */
487 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_cache_direct_map_disable(xqspi_regs_t *XQSPIx)
488 {
489  CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIRECT_MAP_EN);
490  __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
491 }
492 
493 /**
494  * @brief Check if cache direct map function is enabled
495  *
496  * Register|BitsName
497  * --------|--------
498  * CTRL0 |DIRECT_MAP
499  *
500  * @param XQSPIx XQSPI instance
501  * @retval State of bit (1 or 0).
502  */
503 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_cache_direct_map_is_enabled(xqspi_regs_t *XQSPIx)
504 {
505  return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIRECT_MAP_EN));
506 }
507 
508 /**
509  * @brief Enable tag memory flush
510  * @note This bit should not be changed when XIP is ongoing.
511  *
512  * Register|BitsName
513  * --------|--------
514  * CTRL0 |TAG
515  *
516  * @param XQSPIx XQSPI instance
517  * @retval None
518  */
519 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
520 {
521  SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
522 }
523 
524 /**
525  * @brief Disable tag memory flush
526  * @note This bit should not be changed when XIP is ongoing.
527  *
528  * Register|BitsName
529  * --------|--------
530  * CTRL0 |TAG
531  *
532  * @param XQSPIx XQSPI instance
533  * @retval None
534  */
535 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
536 {
537  CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
538 }
539 
540 /**
541  * @brief Check if tag memory flush is enabled
542  *
543  * Register|BitsName
544  * --------|--------
545  * CTRL0 |TAG
546  *
547  * @param XQSPIx XQSPI instance
548  * @retval State of bit (1 or 0).
549  */
550 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
551 {
552  return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH) == (XQSPI_CACHE_CTRL0_FLUSH));
553 }
554 
555 /**
556  * @brief Set cache gating dynamically
557  *
558  * Register|BitsName
559  * --------|--------
560  * CTRL0 |CLK_FORCE_EN
561  *
562  * @param XQSPIx XQSPI instance
563  * @retval None
564  */
565 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_clk_force_en(xqspi_regs_t *XQSPIx)
566 {
567  MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_CLK_FORCE_EN, XQSPI_CACHE_CTRL0_CLK_FORCE_EN);
568 }
569 
570 /**
571  * @brief Set FIFO mode
572  * @note This bit should not be changed when XIP is ongoing.
573  *
574  * Register|BitsName
575  * --------|--------
576  * CTRL0 |FIFO
577  *
578  * @param XQSPIx XQSPI instance
579  * @param mode This parameter can be one of the following values:
580  * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
581  * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
582  * @retval None
583  */
584 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
585 {
586  MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO, mode);
587 }
588 
589 /**
590  * @brief Get FIFO mode
591  * @note This bit should not be changed when XIP is ongoing.
592  *
593  * Register|BitsName
594  * --------|--------
595  * CTRL0 |FIFO
596  *
597  * @param XQSPIx XQSPI instance
598  * @retval Returned Value can be one of the following values:
599  * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
600  * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
601  */
602 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
603 {
604  return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO));
605 }
606 
607 /**
608  * @brief Set HIT/MISS mode
609  * @note This bit should not be changed when XIP is ongoing.
610  *
611  * Register|BitsName
612  * --------|--------
613  * CTRL0 |HITMISS
614  *
615  * @param XQSPIx XQSPI instance
616  * @param mode This parameter can be one of the following values:
617  * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
618  * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
619  * @retval None
620  */
621 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
622 {
623  MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS, mode);
624 }
625 
626 /**
627  * @brief Get HIT/MISS mode
628  * @note This bit should not be changed when XIP is ongoing.
629  *
630  * Register|BitsName
631  * --------|--------
632  * CTRL0 |HITMISS
633  *
634  * @param XQSPIx XQSPI instance
635  * @retval Returned Value can be one of the following values:
636  * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
637  * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
638  */
639 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
640 {
641  return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS));
642 }
643 
644 /**
645  * @brief Set debugbus configurations signals
646  * @note These bits should not be changed when XIP is ongoing.
647  *
648  * Register|BitsName
649  * --------|--------
650  * CTRL1 |DBGBUS_SEL
651  *
652  * @param XQSPIx XQSPI instance
653  * @param sel This parameter can between: 0 ~ 0x7
654  * @retval None
655  */
656 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
657 {
658  MODIFY_REG(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL, sel << XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
659 }
660 
661 /**
662  * @brief Get debugbus configurations signals
663  *
664  * Register|BitsName
665  * --------|--------
666  * CTRL1 |DBGBUS_SEL
667  *
668  * @param XQSPIx XQSPI instance
669  * @retval Returned Value can between: 0 ~ 0x7
670  */
671 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
672 {
673  return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL) >> XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
674 }
675 
676 /**
677  * @brief Enable debug bus mux
678  * @note This bit should not be changed when XIP is ongoing.
679  *
680  * Register|BitsName
681  * --------|--------
682  * CTRL1 |DBGMUX_EN
683  *
684  * @param XQSPIx XQSPI instance
685  * @retval None
686  */
687 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
688 {
689  CLEAR_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
690 }
691 
692 /**
693  * @brief Disable debug bus mux
694  * @note This bit should not be changed when XIP is ongoing.
695  *
696  * Register|BitsName
697  * --------|--------
698  * CTRL1 |DBGMUX_EN
699  *
700  * @param XQSPIx XQSPI instance
701  * @retval None
702  */
703 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
704 {
705  SET_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
706 }
707 
708 /**
709  * @brief Check if debug bus mux is enabled
710  *
711  * Register|BitsName
712  * --------|--------
713  * CTRL1 |DBGMUX_EN
714  *
715  * @param XQSPIx XQSPI instance
716  * @retval State of bit (1 or 0).
717  */
718 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
719 {
720  return (READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN) != (XQSPI_CACHE_CTRL1_DBGMUX_EN));
721 }
722 
723 /**
724  * @brief Get hit counter
725  * @note This bit only be read.
726  *
727  * Register|BitsName
728  * --------|--------
729  * HIT_COUNT|HITCOUNT
730  *
731  * @param XQSPIx XQSPI instance
732  * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
733  */
734 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
735 {
736  return (uint32_t)(READ_REG(XQSPIx->CACHE.HIT_COUNT));
737 }
738 
739 /**
740  * @brief Get miss counter
741  * @note This bit only be read.
742  *
743  * Register|BitsName
744  * --------|--------
745  * MISS_COUNT|MISSCOUNT
746  *
747  * @param XQSPIx XQSPI instance
748  * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
749  */
750 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
751 {
752  return (uint32_t)(READ_REG(XQSPIx->CACHE.MISS_COUNT));
753 }
754 
755 /**
756  * @brief Get cache status
757  * @note This bit only be read.
758  *
759  * Register|BitsName
760  * --------|--------
761  * STAT |STAT
762  *
763  * @param XQSPIx XQSPI instance
764  * @retval Returned Value can between: 0 ~ 1
765  */
766 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
767 {
768  return (uint32_t)(READ_BITS(XQSPIx->CACHE.STAT, XQSPI_CACHE_STAT));
769 }
770 
771 /** @} */
772 
773 /** @defgroup XQSPI_LL_XIP_Configuration XIP LL driver functions
774  * @{
775  */
776 
777 /**
778  * @brief Set read command
779  * @note These bits should not be changed when XIP is ongoing.
780  *
781  * Register|BitsName
782  * --------|--------
783  * CTRL0 |CFG_CMD
784  *
785  * @param XQSPIx XQSPI instance
786  * @param cmd This parameter can be one of the following values:
787  * @arg @ref LL_XQSPI_XIP_CMD_READ
788  * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
789  * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
790  * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
791  * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
792  * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
793  * @retval None
794  */
795 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
796 {
797  MODIFY_REG(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD, cmd);
798 }
799 
800 /**
801  * @brief Get read command
802  *
803  * Register|BitsName
804  * --------|--------
805  * CTRL0 |CFG_CMD
806  *
807  * @param XQSPIx XQSPI instance
808  * @retval Returned Value can be one of the following values:
809  * @arg @ref LL_XQSPI_XIP_CMD_READ
810  * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
811  * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
812  * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
813  * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
814  * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
815  */
816 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
817 {
818  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD));
819 }
820 
821 /**
822  * @brief Enable high performance mode
823  * @note This bit should not be changed when XIP is ongoing.
824  *
825  * Register|BitsName
826  * --------|--------
827  * CTRL1 |CFG_HPEN
828  *
829  * @param XQSPIx XQSPI instance
830  * @retval None
831  */
832 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
833 {
834  SET_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
835 }
836 
837 /**
838  * @brief Enable xqspi soft response request
839  *
840  * Register |BitsName
841  * -----------|------------------
842  * SOFT_RST |XQSPI_XIP_SOFT_RST
843  *
844  * @param XQSPIx XQSPI instance
845  * @retval None
846  */
847 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_soft_rst_req(xqspi_regs_t *XQSPIx)
848 {
849  SET_BITS(XQSPIx->XIP.SOFT_RST, XQSPI_XIP_SOFT_RST);
850 }
851 
852 /**
853  * @brief Disable high performance mode
854  * @note This bit should not be changed when XIP is ongoing.
855  *
856  * Register|BitsName
857  * --------|--------
858  * CTRL1 |CFG_HPEN
859  *
860  * @param XQSPIx XQSPI instance
861  * @retval None
862  */
863 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
864 {
865  CLEAR_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
866 }
867 
868 /**
869  * @brief Check if high performance mode is enabled
870  *
871  * Register|BitsName
872  * --------|--------
873  * CTRL1 |CFG_HPEN
874  *
875  * @param XQSPIx XQSPI instance
876  * @retval State of bit (1 or 0).
877  */
878 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
879 {
880  return (READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN) == (XQSPI_XIP_CFG_HPEN));
881 }
882 
883 /**
884  * @brief Set slave select
885  * @note These bits should not be changed when XIP is ongoing.
886  *
887  * Register|BitsName
888  * --------|--------
889  * CTRL1 |CFG_SS
890  *
891  * @param XQSPIx XQSPI instance
892  * @param ss This parameter can be one or more of the following values:
893  * @arg @ref LL_XQSPI_XIP_SS0
894  * @arg @ref LL_XQSPI_XIP_SS1
895  * @arg @ref LL_XQSPI_XIP_SS2
896  * @arg @ref LL_XQSPI_XIP_SS3
897  * @retval None
898  */
899 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
900 {
901  MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS, ss);
902 }
903 
904 /**
905  * @brief Get slave select
906  *
907  * Register|BitsName
908  * --------|--------
909  * CTRL1 |CFG_SS
910  *
911  * @param XQSPIx XQSPI instance
912  * @retval Returned Value can be one of the following values:
913  * @arg @ref LL_XQSPI_XIP_SS0
914  * @arg @ref LL_XQSPI_XIP_SS1
915  * @arg @ref LL_XQSPI_XIP_SS2
916  * @arg @ref LL_XQSPI_XIP_SS3
917  */
918 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
919 {
920  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS));
921 }
922 
923 /**
924  * @brief Set clock phase
925  * @note This bit should not be changed when XIP is ongoing.
926  *
927  * Register|BitsName
928  * --------|--------
929  * CTRL1 |CFG_CPHA
930  *
931  * @param XQSPIx XQSPI instance
932  * @param cpha This parameter can be one or more of the following values:
933  * @arg @ref LL_XQSPI_SCPHA_1EDGE
934  * @arg @ref LL_XQSPI_SCPHA_2EDGE
935  * @retval None
936  */
937 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
938 {
939  MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA, cpha << XQSPI_XIP_CFG_CPHA_Pos);
940 }
941 
942 /**
943  * @brief Get clock phase
944  *
945  * Register|BitsName
946  * --------|--------
947  * CTRL1 |CFG_CPHA
948  *
949  * @param XQSPIx XQSPI instance
950  * @retval Returned Value can be one of the following values:
951  * @arg @ref LL_XQSPI_SCPHA_1EDGE
952  * @arg @ref LL_XQSPI_SCPHA_2EDGE
953  */
954 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
955 {
956  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA) >> XQSPI_XIP_CFG_CPHA_Pos);
957 }
958 
959 /**
960  * @brief Set clock polarity
961  * @note This bit should not be changed when XIP is ongoing.
962  *
963  * Register|BitsName
964  * --------|--------
965  * CTRL1 |CFG_CPOL
966  *
967  * @param XQSPIx XQSPI instance
968  * @param cpol This parameter can be one or more of the following values:
969  * @arg @ref LL_XQSPI_SCPOL_LOW
970  * @arg @ref LL_XQSPI_SCPOL_HIGH
971  * @retval None
972  */
973 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
974 {
975  MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL, cpol << XQSPI_XIP_CFG_CPOL_Pos);
976 }
977 
978 /**
979  * @brief Get clock polarity
980  *
981  * Register|BitsName
982  * --------|--------
983  * CTRL1 |CFG_CPOL
984  *
985  * @param XQSPIx XQSPI instance
986  * @retval Returned Value can be one of the following values:
987  * @arg @ref LL_XQSPI_SCPOL_LOW
988  * @arg @ref LL_XQSPI_SCPOL_HIGH
989  */
990 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
991 {
992  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL) >> XQSPI_XIP_CFG_CPOL_Pos);
993 }
994 
995 /**
996  * @brief Set address bytes in command
997  * @note This bit should not be changed when XIP is ongoing.
998  *
999  * Register|BitsName
1000  * --------|--------
1001  * CTRL1 |CFG_ADDR4
1002  *
1003  * @param XQSPIx XQSPI instance
1004  * @param size This parameter can be one or more of the following values:
1005  * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
1006  * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
1007  * @retval None
1008  */
1009 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
1010 {
1011  MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4, size);
1012 }
1013 
1014 /**
1015  * @brief Get address bytes in command
1016  *
1017  * Register|BitsName
1018  * --------|--------
1019  * CTRL1 |CFG_ADDR4
1020  *
1021  * @param XQSPIx XQSPI instance
1022  * @retval Returned Value can be one of the following values:
1023  * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
1024  * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
1025  */
1026 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
1027 {
1028  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4));
1029 }
1030 
1031 /**
1032  * @brief Set endian in reading data
1033  * @note This bit should not be changed when XIP is ongoing.
1034  *
1035  * Register|BitsName
1036  * --------|--------
1037  * CTRL1 |CFG_LE32
1038  *
1039  * @param XQSPIx XQSPI instance
1040  * @param endian This parameter can be one or more of the following values:
1041  * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
1042  * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
1043  * @retval None
1044  */
1045 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
1046 {
1047  MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32, endian);
1048 }
1049 
1050 /**
1051  * @brief Get endian in reading data
1052  *
1053  * Register|BitsName
1054  * --------|--------
1055  * CTRL1 |CFG_LE32
1056  *
1057  * @param XQSPIx XQSPI instance
1058  * @retval Returned Value can be one of the following values:
1059  * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
1060  * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
1061  */
1062 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
1063 {
1064  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32));
1065 }
1066 
1067 /**
1068  * @brief Set high performance command
1069  * @note These bits should not be changed when XIP is ongoing.
1070  *
1071  * Register|BitsName
1072  * --------|--------
1073  * CTRL2 |CFG_HPMODE
1074  *
1075  * @param XQSPIx XQSPI instance
1076  * @param cmd This value is specified by different QSPI FLASH memory vendor to enter into its status register
1077  * to activate HP mode in dual I/O and Quad I/O access. This parameter can between: 0 ~ 0xFF.
1078  * @retval None
1079  */
1080 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
1081 {
1082  MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE, cmd << XQSPI_XIP_CFG_HPMODE_Pos);
1083 }
1084 
1085 /**
1086  * @brief Get high performance command
1087  *
1088  * Register|BitsName
1089  * --------|--------
1090  * CTRL2 |CFG_HPMODE
1091  *
1092  * @param XQSPIx XQSPI instance
1093  * @retval Returned Value can between: 0 ~ 0xFF.
1094  */
1095 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
1096 {
1097  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE) >> XQSPI_XIP_CFG_HPMODE_Pos);
1098 }
1099 
1100 /**
1101  * @brief Set dummy cycles in command
1102  * @note These bits should not be changed when XIP is ongoing.
1103  * - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
1104  * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
1105  * - Fast Read Dual Out: dummycycles = 8 * cycles
1106  * - Fast Read Quad Out: dummycycles = 8 * cycles
1107  *
1108  * Register|BitsName
1109  * --------|--------
1110  * CTRL2 |CFG_DUMMYCYCLES
1111  *
1112  * @param XQSPIx XQSPI instance
1113  * @param cycles This parameter can between: 0 ~ 0xF.
1114  * @retval None
1115  */
1116 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
1117 {
1118  MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES, cycles << XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
1119 }
1120 
1121 /**
1122  * @brief Get dummy cycles in command
1123  * @note - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
1124  * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
1125  * - Fast Read Dual Out: dummycycles = 8 * cycles
1126  * - Fast Read Quad Out: dummycycles = 8 * cycles
1127  *
1128  * Register|BitsName
1129  * --------|--------
1130  * CTRL2 |CFG_DUMMYCYCLES
1131  *
1132  * @param XQSPIx XQSPI instance
1133  * @retval Returned Value can between: 0 ~ 0xF.
1134  */
1135 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
1136 {
1137  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES) >> XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
1138 }
1139 /**
1140  * @brief Set dummy cycles in high performance end
1141  * @note These bits should not be changed when XIP is ongoing.
1142  *
1143  * Register|BitsName
1144  * --------|--------
1145  * CTRL2 |CFG_ENDDUMMY
1146  *
1147  * @param XQSPIx XQSPI instance
1148  * @param cycles This parameter can between: 0 ~ 3.
1149  * @retval None
1150  */
1151 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
1152 {
1153  MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY, cycles << XQSPI_XIP_CFG_ENDDUMMY_Pos);
1154 }
1155 
1156 /**
1157  * @brief Get dummy cycles in high performance end
1158  *
1159  * Register|BitsName
1160  * --------|--------
1161  * CTRL2 |CFG_ENDDUMMY
1162  *
1163  * @param XQSPIx XQSPI instance
1164  * @retval Returned Value can between: 0 ~ 3.
1165  */
1166 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
1167 {
1168  return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY) >> XQSPI_XIP_CFG_ENDDUMMY_Pos);
1169 }
1170 
1171 /**
1172  * @brief Enable XIP mode
1173  *
1174  * Register|BitsName
1175  * --------|--------
1176  * CTRL3 |EN_REQ
1177  *
1178  * @param XQSPIx XQSPI instance
1179  * @retval None
1180  */
1181 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
1182 {
1183  SET_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1184 }
1185 
1186 /**
1187  * @brief Disable XIP mode
1188  *
1189  * Register|BitsName
1190  * --------|--------
1191  * CTRL3 |EN_REQ
1192  *
1193  * @param XQSPIx XQSPI instance
1194  * @retval None
1195  */
1196 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
1197 {
1198  CLEAR_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1199 }
1200 
1201 /**
1202  * @brief Check if XIP mode is enabled
1203  * @note This bit should not be changed when XIP is ongoing.
1204  *
1205  * Register|BitsName
1206  * --------|--------
1207  * CTRL3 |EN_REQ
1208  *
1209  * @param XQSPIx XQSPI instance
1210  * @retval State of bit (1 or 0).
1211  */
1212 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
1213 {
1214  return (READ_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ) == (XQSPI_XIP_EN_REQ));
1215 }
1216 
1217 /**
1218  * @brief Get XIP status
1219  * @note This bit is read-only.
1220  *
1221  * Register|BitsName
1222  * --------|--------
1223  * STAT |EN_OUT
1224  *
1225  * @param XQSPIx XQSPI instance
1226  * @retval Returned Value can between: 0 ~ 1
1227  */
1228 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
1229 {
1230  return (uint32_t)(READ_BITS(XQSPIx->XIP.STAT, XQSPI_XIP_EN_OUT));
1231 }
1232 
1233 /**
1234  * @brief Check if XIP interrupt is enabled
1235  * @note This bit is read-only.
1236  *
1237  * Register|BitsName
1238  * --------|--------
1239  * INTEN |INT_EN
1240  *
1241  * @param XQSPIx XQSPI instance
1242  * @retval Returned Value can between: 0 ~ 1
1243  */
1244 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
1245 {
1246  return (uint32_t)(READ_BITS(XQSPIx->XIP.INTEN, XQSPI_XIP_INT_EN));
1247 }
1248 
1249 /**
1250  * @brief Get XIP interrupt flag
1251  * @note This bit is read-only.
1252  *
1253  * Register|BitsName
1254  * --------|--------
1255  * INTSTAT |INT_STAT
1256  *
1257  * @param XQSPIx XQSPI instance
1258  * @retval Returned Value can between: 0 ~ 1
1259  */
1260 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
1261 {
1262  return (uint32_t)(READ_BITS(XQSPIx->XIP.INTSTAT, XQSPI_XIP_INT_STAT));
1263 }
1264 
1265 /**
1266  * @brief Get XIP interrupt request
1267  * @note This bit is read-only.
1268  *
1269  * Register|BitsName
1270  * --------|--------
1271  * INTREQ |INT_REQ
1272  *
1273  * @param XQSPIx XQSPI instance
1274  * @retval Returned Value can between: 0 ~ 1
1275  */
1276 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
1277 {
1278  return (uint32_t)(READ_BITS(XQSPIx->XIP.INTREQ, XQSPI_XIP_INT_REQ));
1279 }
1280 
1281 /**
1282  * @brief Set XIP interrupt enable
1283  * @note This bit is write-only.
1284  *
1285  * Register|BitsName
1286  * --------|--------
1287  * INTSET |INT_SET
1288  *
1289  * @param XQSPIx XQSPI instance
1290  * @retval None
1291  */
1292 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
1293 {
1294  SET_BITS(XQSPIx->XIP.INTSET, XQSPI_XIP_INT_SET);
1295 }
1296 
1297 /**
1298  * @brief Set XIP interrupt disable
1299  * @note This bit is write-only.
1300  *
1301  * Register|BitsName
1302  * --------|--------
1303  * INTCLR |INT_CLR
1304  *
1305  * @param XQSPIx XQSPI instance
1306  * @retval None
1307  */
1308 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
1309 {
1310  SET_BITS(XQSPIx->XIP.INTCLR, XQSPI_XIP_INT_CLR);
1311 }
1312 
1313 /** @} */
1314 
1315 /** @defgroup XQSPI_LL_QSPI_Configuration QSPI driver functions
1316  * @{
1317  */
1318 
1319 /**
1320  * @brief Write 8-bit in the data register
1321  *
1322  * Register|BitsName
1323  * --------|--------
1324  * TX_DATA | DATA
1325  *
1326  * @param XQSPIx XQSPI instance
1327  * @param tx_data This parameter can between: 0x00 ~ 0xFF
1328  * @retval None
1329  */
1330 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
1331 {
1332  *((__IOM uint8_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1333 }
1334 
1335 /**
1336  * @brief Write 16-bit in the data register
1337  *
1338  * Register|BitsName
1339  * --------|--------
1340  * TX_DATA | DATA
1341  *
1342  * @param XQSPIx XQSPI instance
1343  * @param tx_data This parameter can between: 0x00 ~ 0xFFFF
1344  * @retval None
1345  */
1346 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
1347 {
1348  *((__IOM uint16_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1349 }
1350 
1351 /**
1352  * @brief Write 32-bit in the data register
1353  *
1354  * Register|BitsName
1355  * --------|--------
1356  * TX_DATA | DATA
1357  *
1358  * @param XQSPIx XQSPI instance
1359  * @param tx_data This parameter can between: 0x00 ~ 0xFFFFFFFF
1360  * @retval None
1361  */
1362 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
1363 {
1364  *((__IOM uint32_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1365 }
1366 
1367 /**
1368  * @brief Read 8 bits in the data register
1369  *
1370  * Register|BitsName
1371  * --------|--------
1372  * RX_DATA | DATA
1373  *
1374  * @param XQSPIx XQSPI instance
1375  * @retval Returned Value between: 0x00 ~ 0xFF
1376  */
1377 SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
1378 {
1379  return (uint8_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1380 }
1381 
1382 /**
1383  * @brief Read 16 bits in the data register
1384  *
1385  * Register|BitsName
1386  * --------|--------
1387  * RX_DATA | DATA
1388  *
1389  * @param XQSPIx XQSPI instance
1390  * @retval Returned Value between: 0x00 ~ 0xFFFF
1391  */
1392 SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
1393 {
1394  return (uint16_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1395 }
1396 
1397 /**
1398  * @brief Read 32 bits in the data register
1399  *
1400  * Register|BitsName
1401  * --------|--------
1402  * RX_DATA | DATA
1403  *
1404  * @param XQSPIx XQSPI instance
1405  * @retval Returned Value between: 0x00 ~ 0xFFFFFFFF
1406  */
1407 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
1408 {
1409  return (uint32_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1410 }
1411 
1412 /**
1413  * @brief Set TX FIFO threshold level
1414  * @note FIFO maximum depth is 16 units.
1415  *
1416  * Register|BitsName
1417  * --------|--------
1418  * CTRL |TXWMARK
1419  *
1420  * @param XQSPIx XQSPI instance
1421  * @param threshold This parameter can be one of the following values:
1422  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1423  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1424  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1425  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1426  * @retval None
1427  */
1428 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1429 {
1430  MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK, threshold << XQSPI_QSPI_CTRL_TXWMARK_Pos);
1431 }
1432 
1433 /**
1434  * @brief Get TX FIFO threshold level
1435  * @note FIFO maximum depth is 16 units.
1436  *
1437  * Register|BitsName
1438  * --------|--------
1439  * CTRL |TXWMARK
1440  *
1441  * @param XQSPIx XQSPI instance
1442  * @retval Returned Value can be one of the following values:
1443  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1444  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1445  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1446  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1447  */
1448 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
1449 {
1450  return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK) >> XQSPI_QSPI_CTRL_TXWMARK_Pos);
1451 }
1452 
1453 /**
1454  * @brief Set RX FIFO threshold level
1455  * @note FIFO maximum depth is 16 units.
1456  *
1457  * Register|BitsName
1458  * --------|--------
1459  * CTRL |RXWMARK
1460  *
1461  * @param XQSPIx XQSPI instance
1462  * @param threshold This parameter can be one of the following values:
1463  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1464  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1465  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1466  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1467  * @retval None
1468  */
1469 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1470 {
1471  MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK, threshold << XQSPI_QSPI_CTRL_RXWMARK_Pos);
1472 }
1473 
1474 /**
1475  * @brief Get RX FIFO threshold level
1476  * @note FIFO maximum depth is 16 units.
1477  *
1478  * Register|BitsName
1479  * --------|--------
1480  * CTRL |RXWMARK
1481  *
1482  * @param XQSPIx XQSPI instance
1483  * @retval Returned Value can be one of the following values:
1484  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1485  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1486  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1487  * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1488  */
1489 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
1490 {
1491  return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK) >> XQSPI_QSPI_CTRL_RXWMARK_Pos);
1492 }
1493 
1494 /**
1495  * @brief Enable dummy cycles
1496  *
1497  * Register|BitsName
1498  * --------|--------
1499  * CTRL |MWAITEN
1500  *
1501  * @param XQSPIx XQSPI instance
1502  * @retval None
1503  */
1504 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
1505 {
1506  SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1507 }
1508 
1509 /**
1510  * @brief Disable dummy cycles
1511  *
1512  * Register|BitsName
1513  * --------|--------
1514  * CTRL |MWAITEN
1515  *
1516  * @param XQSPIx XQSPI instance
1517  * @retval None
1518  */
1519 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
1520 {
1521  CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1522 }
1523 
1524 /**
1525  * @brief Check if dummy cycles is enabled
1526  *
1527  * Register|BitsName
1528  * --------|--------
1529  * CTRL |MWAITEN
1530  *
1531  * @param XQSPIx XQSPI instance
1532  * @retval State of bit (1 or 0).
1533  */
1534 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
1535 {
1536  return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN) == (XQSPI_QSPI_CTRL_MWAITEN));
1537 }
1538 
1539 /**
1540  * @brief Enable DMA mode
1541  *
1542  * Register|BitsName
1543  * --------|--------
1544  * CTRL |DMA
1545  *
1546  * @param XQSPIx XQSPI instance
1547  * @retval None
1548  */
1549 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
1550 {
1551  SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1552 }
1553 
1554 /**
1555  * @brief Disable DMA mode
1556  *
1557  * Register|BitsName
1558  * --------|--------
1559  * CTRL |DMA
1560  *
1561  * @param XQSPIx XQSPI instance
1562  * @retval None
1563  */
1564 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
1565 {
1566  CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1567 }
1568 
1569 /**
1570  * @brief Check if DMA mode is enabled
1571  *
1572  * Register|BitsName
1573  * --------|--------
1574  * CTRL |DMA
1575  *
1576  * @param XQSPIx XQSPI instance
1577  * @retval State of bit (1 or 0).
1578  */
1579 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
1580 {
1581  return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA) == (XQSPI_QSPI_CTRL_DMA));
1582 }
1583 
1584 /**
1585  * @brief Set clock polarity
1586  * @note This bit should not be changed when communication is ongoing.
1587  *
1588  * Register|BitsName
1589  * --------|--------
1590  * CTRL |CPOL
1591  *
1592  * @param XQSPIx XQSPI instance
1593  * @param cpol This parameter can be one of the following values:
1594  * @arg @ref LL_XQSPI_SCPOL_LOW
1595  * @arg @ref LL_XQSPI_SCPOL_HIGH
1596  * @retval None
1597  */
1598 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
1599 {
1600  MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL, cpol << XQSPI_QSPI_CTRL_CPOL_Pos);
1601 }
1602 
1603 /**
1604  * @brief Get clock polarity
1605  *
1606  * Register|BitsName
1607  * --------|--------
1608  * CTRL |CPOL
1609  *
1610  * @param XQSPIx XQSPI instance
1611  * @retval Returned Value can be one of the following values:
1612  * @arg @ref LL_XQSPI_SCPOL_LOW
1613  * @arg @ref LL_XQSPI_SCPOL_HIGH
1614  */
1615 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
1616 {
1617  return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL) >> XQSPI_QSPI_CTRL_CPOL_Pos);
1618 }
1619 
1620 /**
1621  * @brief Set clock phase
1622  * @note This bit should not be changed when communication is ongoing.
1623  *
1624  * Register|BitsName
1625  * --------|--------
1626  * CTRL |CPHA
1627  *
1628  * @param XQSPIx XQSPI instance
1629  * @param cpha This parameter can be one of the following values:
1630  * @arg @ref LL_XQSPI_SCPHA_1EDGE
1631  * @arg @ref LL_XQSPI_SCPHA_2EDGE
1632  * @retval None
1633  */
1634 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
1635 {
1636  MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA, cpha << XQSPI_QSPI_CTRL_CPHA_Pos);
1637 }
1638 
1639 /**
1640  * @brief Get clock phase
1641  *
1642  * Register|BitsName
1643  * --------|--------
1644  * CTRL |CPHA
1645  *
1646  * @param XQSPIx XQSPI instance
1647  * @retval Returned Value can be one of the following values:
1648  * @arg @ref LL_XQSPI_SCPHA_1EDGE
1649  * @arg @ref LL_XQSPI_SCPHA_2EDGE
1650  */
1651 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
1652 {
1653  return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA) >> XQSPI_QSPI_CTRL_CPHA_Pos);
1654 }
1655 
1656 /**
1657  * @brief Set serial data order
1658  *
1659  * Register|BitsName
1660  * --------|--------
1661  * CTRL |MSB1ST
1662  *
1663  * @param XQSPIx XQSPI instance
1664  * @param order This parameter can be one of the following values:
1665  * @arg @ref LL_XQSPI_QSPI_LSB
1666  * @arg @ref LL_XQSPI_QSPI_MSB
1667  * @retval None
1668  */
1669 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
1670 {
1671  MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST, order);
1672 }
1673 
1674 /**
1675  * @brief Get serial data order
1676  *
1677  * Register|BitsName
1678  * --------|--------
1679  * CTRL |MSB1ST
1680  *
1681  * @param XQSPIx XQSPI instance
1682  * @retval Returned Value can be one of the following values:
1683  * @arg @ref LL_XQSPI_QSPI_LSB
1684  * @arg @ref LL_XQSPI_QSPI_MSB
1685  */
1686 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
1687 {
1688  return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST));
1689 }
1690 
1691 /**
1692  * @brief Enable continuous transfer mode
1693  *
1694  * Register|BitsName
1695  * --------|--------
1696  * CTRL |CONTXFER
1697  *
1698  * @param XQSPIx XQSPI instance
1699  * @retval None
1700  */
1701 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1702 {
1703  SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1704 }
1705 
1706 /**
1707  * @brief Disable continuous transfer mode
1708  *
1709  * Register|BitsName
1710  * --------|--------
1711  * CTRL |CONTXFER
1712  *
1713  * @param XQSPIx XQSPI instance
1714  * @retval None
1715  */
1716 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1717 {
1718  CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1719 }
1720 
1721 /**
1722  * @brief Check if continuous transfer mode is enabled
1723  *
1724  * Register|BitsName
1725  * --------|--------
1726  * CTRL |CONTXFER
1727  *
1728  * @param XQSPIx XQSPI instance
1729  * @retval State of bit (1 or 0).
1730  */
1731 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
1732 {
1733  return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER) == (XQSPI_QSPI_CTRL_CONTXFER));
1734 }
1735 
1736 /**
1737  * @brief Enable continuous transfer extend mode
1738  *
1739  * Register|BitsName
1740  * --------|--------
1741  * AUX_CTRL|CONTXFERX
1742  *
1743  * @param XQSPIx XQSPI instance
1744  * @retval None
1745  */
1746 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1747 {
1748  SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1749 }
1750 
1751 /**
1752  * @brief Disable continuous transfer extend mode
1753  *
1754  * Register|BitsName
1755  * --------|--------
1756  * AUX_CTRL|CONTXFERX
1757  *
1758  * @param XQSPIx XQSPI instance
1759  * @retval None
1760  */
1761 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1762 {
1763  CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1764 }
1765 
1766 /**
1767  * @brief Check if continuous transfer extend mode is enabled
1768  *
1769  * Register|BitsName
1770  * --------|--------
1771  * AUX_CTRL|CONTXFERX
1772  *
1773  * @param XQSPIx XQSPI instance
1774  * @retval State of bit (1 or 0).
1775  */
1776 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1777 {
1778  return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX) == (XQSPI_QSPI_AUXCTRL_CONTXFERX));
1779 }
1780 
1781 /**
1782  * @brief Set data size
1783  * @note These bits should not be changed when communication is ongoing.
1784  *
1785  * Register|BitsName
1786  * --------|--------
1787  * AUX_CTRL|BITSIZE
1788  *
1789  * @param XQSPIx XQSPI instance
1790  * @param szie This parameter can be one of the following values:
1791  * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1792  * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1793  * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1794  * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1795  * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1796  * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1797  * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1798  * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1799  * @retval None
1800  */
1801 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
1802 {
1803  MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE, szie);
1804 }
1805 
1806 /**
1807  * @brief Get data size
1808  *
1809  * Register|BitsName
1810  * --------|--------
1811  * AUX_CTRL|BITSIZE
1812  *
1813  * @param XQSPIx XQSPI instance
1814  * @retval Returned Value can be one of the following values:
1815  * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1816  * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1817  * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1818  * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1819  * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1820  * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1821  * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1822  * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1823  */
1824 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
1825 {
1826  return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE));
1827 }
1828 
1829 /**
1830  * @brief Enable inhibt data input to RX FIFO
1831  *
1832  * Register|BitsName
1833  * --------|--------
1834  * AUX_CTRL|INHIBITDIN
1835  *
1836  * @param XQSPIx XQSPI instance
1837  * @retval None
1838  */
1839 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
1840 {
1841  SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1842 }
1843 
1844 /**
1845  * @brief Disable inhibt data input to RX FIFO
1846  *
1847  * Register|BitsName
1848  * --------|--------
1849  * AUX_CTRL|INHIBITDIN
1850  *
1851  * @param XQSPIx XQSPI instance
1852  * @retval None
1853  */
1854 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
1855 {
1856  CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1857 }
1858 
1859 /**
1860  * @brief Check if inhibt data input to RX FIFO is enabled
1861  *
1862  * Register|BitsName
1863  * --------|--------
1864  * AUX_CTRL|INHIBITDIN
1865  *
1866  * @param XQSPIx XQSPI instance
1867  * @retval State of bit (1 or 0).
1868  */
1869 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
1870 {
1871  return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN) == XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1872 }
1873 
1874 /**
1875  * @brief Enable inhibt data output to TX FIFO
1876  *
1877  * Register|BitsName
1878  * --------|--------
1879  * AUX_CTRL|INHIBITDOUT
1880  *
1881  * @param XQSPIx XQSPI instance
1882  * @retval None
1883  */
1884 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
1885 {
1886  SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1887 }
1888 
1889 /**
1890  * @brief Disable inhibt data output to TX FIFO
1891  *
1892  * Register|BitsName
1893  * --------|--------
1894  * AUX_CTRL|INHIBITDOUT
1895  *
1896  * @param XQSPIx XQSPI instance
1897  * @retval None
1898  */
1899 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
1900 {
1901  CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1902 }
1903 
1904 /**
1905  * @brief Check if inhibt data input to TX FIFO is enabled
1906  *
1907  * Register|BitsName
1908  * --------|--------
1909  * AUX_CTRL|INHIBITDOUT
1910  *
1911  * @param XQSPIx XQSPI instance
1912  * @retval State of bit (1 or 0).
1913  */
1914 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
1915 {
1916  return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT) == XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1917 }
1918 
1919 /**
1920  * @brief Set frame format
1921  * @note These bits should not be changed when communication is ongoing.
1922  *
1923  * Register|BitsName
1924  * --------|--------
1925  * AUX_CTRL|QMODE
1926  *
1927  * @param XQSPIx XQSPI instance
1928  * @param format This parameter can be one of the following values:
1929  * @arg @ref LL_XQSPI_QSPI_FRF_SPI
1930  * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
1931  * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
1932  * @retval None
1933  */
1934 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
1935 {
1936  MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE, format);
1937 }
1938 
1939 /**
1940  * @brief Get frame format
1941  *
1942  * Register|BitsName
1943  * --------|--------
1944  * AUX_CTRL|QMODE
1945  *
1946  * @param XQSPIx XQSPI instance
1947  * @retval Returned Value can be one even value:
1948  * @arg @ref LL_XQSPI_QSPI_FRF_SPI
1949  * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
1950  * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
1951  */
1952 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
1953 {
1954  return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE));
1955 }
1956 
1957 /**
1958  * @brief Get QSPI status
1959  *
1960  * Register|BitsName
1961  * --------|--------
1962  * STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP
1963  *
1964  * @param XQSPIx XQSPI instance
1965  * @retval Returned Value can be one or combination of the following values:
1966  * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
1967  * @arg @ref LL_XQSPI_QSPI_STAT_RFF
1968  * @arg @ref LL_XQSPI_QSPI_STAT_RFE
1969  * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
1970  * @arg @ref LL_XQSPI_QSPI_STAT_TFF
1971  * @arg @ref LL_XQSPI_QSPI_STAT_TFE
1972  * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
1973  */
1974 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
1975 {
1976  return (uint32_t)(READ_REG(XQSPIx->QSPI.STAT));
1977 }
1978 
1979 /**
1980  * @brief Check active flag
1981  *
1982  * Register|BitsName
1983  * --------|--------
1984  * STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP
1985  *
1986  * @param XQSPIx XQSPI instance
1987  * @param flag This parameter can be one of the following values:
1988  * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
1989  * @arg @ref LL_XQSPI_QSPI_STAT_RFF
1990  * @arg @ref LL_XQSPI_QSPI_STAT_RFE
1991  * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
1992  * @arg @ref LL_XQSPI_QSPI_STAT_TFF
1993  * @arg @ref LL_XQSPI_QSPI_STAT_TFE
1994  * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
1995  * @retval State of bit (1 or 0).
1996  */
1997 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
1998 {
1999  return (READ_BITS(XQSPIx->QSPI.STAT, flag) == (flag));
2000 }
2001 
2002 /**
2003  * @brief Enable slave select output
2004  *
2005  * Register|BitsName
2006  * --------|--------
2007  * SLAVE_SEL|OUT3 OUT2 OUT1 OUT0
2008  *
2009  * @param XQSPIx XQSPI instance
2010  * @param ssout This parameter can between: 0 ~ 0xFF
2011  * @retval None
2012  */
2013 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
2014 {
2015  SET_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
2016 }
2017 
2018 /**
2019  * @brief Disable slave select output
2020  *
2021  * Register|BitsName
2022  * --------|--------
2023  * SLAVE_SEL|OUT3 OUT2 OUT1 OUT0
2024  *
2025  * @param XQSPIx XQSPI instance
2026  * @param ssout This parameter can between: 0 ~ 0xFF
2027  * @retval None
2028  */
2029 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
2030 {
2031  CLEAR_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
2032 }
2033 
2034 /**
2035  * @brief Set slave select output polarity
2036  *
2037  * Register|BitsName
2038  * --------|--------
2039  * SLAVE_SEL_POL|POL3 POL2 POL1 POL0
2040  *
2041  * @param XQSPIx XQSPI instance
2042  * @param sspol This parameter can between: 0 ~ 0xFF
2043  * @retval None
2044  */
2045 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
2046 {
2047  SET_BITS(XQSPIx->QSPI.SLAVE_SEL_POL, sspol);
2048 }
2049 
2050 /**
2051  * @brief Get slave select output polarity
2052  *
2053  * Register|BitsName
2054  * --------|--------
2055  * SLAVE_SEL_POL|POL3 POL2 POL1 POL0
2056  *
2057  * @param XQSPIx XQSPI instance
2058  * @retval Returned Value can between: 0 ~ 0xFF
2059  */
2060 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
2061 {
2062  return (uint32_t)(READ_REG(XQSPIx->QSPI.SLAVE_SEL_POL));
2063 }
2064 
2065 /**
2066  * @brief Get FIFO Transmission Level
2067  *
2068  * Register|BitsName
2069  * --------|--------
2070  * TX_FIFO_LVL | TXFIFOLVL
2071  *
2072  * @param XQSPIx XQSPI instance
2073  * @retval Returned Value can between: 0 ~ 16
2074  */
2075 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
2076 {
2077  return (uint32_t)(READ_BITS(XQSPIx->QSPI.TX_FIFO_LVL, XQSPI_QSPI_TXFIFOLVL));
2078 }
2079 
2080 /**
2081  * @brief Get FIFO reception Level
2082  *
2083  * Register|BitsName
2084  * --------|--------
2085  * RX_FIFO_LVL | RXFIFOLVL
2086  *
2087  * @param XQSPIx XQSPI instance
2088  * @retval Returned Value can between: 0 ~ 16
2089  */
2090 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
2091 {
2092  return (uint32_t)(READ_BITS(XQSPIx->QSPI.RX_FIFO_LVL, XQSPI_QSPI_RXFIFOLVL));
2093 }
2094 
2095 /**
2096  * @brief Enable interrupt
2097  * @note This bit controls the generation of an interrupt when an event occurs.
2098  *
2099  * Register|BitsName
2100  * --------|--------
2101  * INTEN |INT_EN
2102  *
2103  * @param XQSPIx XQSPI instance
2104  * @param mask This parameter can be one of the following values:
2105  * @arg @ref LL_XQSPI_QSPI_IM_DONE
2106  * @arg @ref LL_XQSPI_QSPI_IM_RFF
2107  * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2108  * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2109  * @arg @ref LL_XQSPI_QSPI_IM_TFE
2110  * @retval None
2111  */
2112 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2113 {
2114  SET_BITS(XQSPIx->QSPI.INTEN, mask);
2115 }
2116 
2117 /**
2118  * @brief Disable interrupt
2119  * @note This bit controls the generation of an interrupt when an event occurs.
2120  *
2121  * Register|BitsName
2122  * --------|--------
2123  * INTEN |INT_EN
2124  *
2125  * @param XQSPIx XQSPI instance
2126  * @param mask This parameter can be one of the following values:
2127  * @arg @ref LL_XQSPI_QSPI_IM_DONE
2128  * @arg @ref LL_XQSPI_QSPI_IM_RFF
2129  * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2130  * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2131  * @arg @ref LL_XQSPI_QSPI_IM_TFE
2132  * @retval None
2133  */
2134 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2135 {
2136  CLEAR_BITS(XQSPIx->QSPI.INTEN, mask);
2137 }
2138 
2139 /**
2140  * @brief Check if interrupt is enabled
2141  *
2142  * Register|BitsName
2143  * --------|--------
2144  * INTEN |INT_EN
2145  *
2146  * @param XQSPIx XQSPI instance
2147  * @param mask This parameter can be one of the following values:
2148  * @arg @ref LL_XQSPI_QSPI_IM_DONE
2149  * @arg @ref LL_XQSPI_QSPI_IM_RFF
2150  * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2151  * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2152  * @arg @ref LL_XQSPI_QSPI_IM_TFE
2153  * @retval State of bit (1 or 0).
2154  */
2155 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2156 {
2157  return (READ_BITS(XQSPIx->QSPI.INTEN, mask) == (mask));
2158 }
2159 
2160 /**
2161  * @brief Get XQSPI interrupt flags
2162  *
2163  * Register|BitsName
2164  * --------|--------
2165  * INTSTAT |INT_STAT
2166  *
2167  * @param XQSPIx XQSPI instance
2168  * @retval Returned Value can be one or combination of the following values:
2169  * @arg @ref LL_XQSPI_QSPI_IS_DONE
2170  * @arg @ref LL_XQSPI_QSPI_IS_RFF
2171  * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2172  * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2173  * @arg @ref LL_XQSPI_QSPI_IS_TFE
2174  */
2175 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
2176 {
2177  return (uint32_t)(READ_REG(XQSPIx->QSPI.INTSTAT));
2178 }
2179 
2180 /**
2181  * @brief Check interrupt flag
2182  *
2183  * Register|BitsName
2184  * --------|--------
2185  * INTSTAT | XFER_DPULSE
2186  * INTSTAT | RX_FPULSE
2187  * INTSTAT | RX_WPULSE
2188  * INTSTAT | TX_WPULSE
2189  * INTSTAT | TX_EPULSE
2190  *
2191  * @param XQSPIx XQSPI instance
2192  * @param flag This parameter can be one of the following values:
2193  * @arg @ref LL_XQSPI_QSPI_IS_DONE
2194  * @arg @ref LL_XQSPI_QSPI_IS_RFF
2195  * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2196  * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2197  * @arg @ref LL_XQSPI_QSPI_IS_TFE
2198  * @retval State of bit (1 or 0).
2199  */
2200 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2201 {
2202  return (READ_BITS(XQSPIx->QSPI.INTSTAT, flag) == (flag));
2203 }
2204 
2205 /**
2206  * @brief Clear interrupt flag
2207  * @note Clearing interrupt flag is done by writting INTCLR register
2208  *
2209  * Register|BitsName
2210  * --------|--------
2211  * INTCLR |INT_CLR
2212  *
2213  * @param XQSPIx XQSPI instance
2214  * @param flag This parameter can be one of the following values:
2215  * @arg @ref LL_XQSPI_QSPI_IM_DONE
2216  * @arg @ref LL_XQSPI_QSPI_IM_RFF
2217  * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2218  * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2219  * @arg @ref LL_XQSPI_QSPI_IM_TFE
2220  * @retval None
2221  */
2222 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2223 {
2224  WRITE_REG(XQSPIx->QSPI.INTCLR, flag);
2225 }
2226 
2227 /**
2228  * @brief Set master inter-transfer delay
2229  *
2230  * Register|BitsName
2231  * --------|--------
2232  * MSTR_IT_DELAY | MWAIT
2233  *
2234  * @param XQSPIx XQSPI instance
2235  * @param wait This parameter can between: 0 ~ 255
2236  * @retval None
2237  */
2238 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
2239 {
2240  MODIFY_REG(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT, wait << XQSPI_QSPI_MWAIT_MWAIT_Pos);
2241 }
2242 
2243 /**
2244  * @brief Get master inter-transfer delay
2245  *
2246  * Register|BitsName
2247  * --------|--------
2248  * MSTR_IT_DELAY | MWAIT
2249  *
2250  * @param XQSPIx XQSPI instance
2251  * @retval Returned Value can between: 0 ~ 255
2252  */
2253 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
2254 {
2255  return (uint32_t)(READ_BITS(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT) >> XQSPI_QSPI_MWAIT_MWAIT_Pos);
2256 }
2257 
2258 /**
2259  * @brief Enable QSPI
2260  * @note This bit should not be enable when XIP is ongoing.
2261  *
2262  * Register|BitsName
2263  * --------|--------
2264  * SPIEN |EN
2265  *
2266  * @param XQSPIx XQSPI instance
2267  * @retval None
2268  */
2269 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
2270 {
2271  SET_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2272 }
2273 
2274 /**
2275  * @brief Disable QSPI
2276  *
2277  * Register|BitsName
2278  * --------|--------
2279  * SPIEN |EN
2280  *
2281  * @param XQSPIx XQSPI instance
2282  * @retval None
2283  */
2284 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
2285 {
2286  CLEAR_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2287 }
2288 
2289 /**
2290  * @brief Check if QSPI is enabled
2291  *
2292  * Register|BitsName
2293  * --------|--------
2294  * SPIEN |EN
2295  *
2296  * @param XQSPIx XQSPI instance
2297  * @retval State of bit (1 or 0).
2298  */
2299 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
2300 {
2301  return (READ_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN) == (XQSPI_QSPI_EN_EN));
2302 }
2303 
2304 /**
2305  * @brief Set QSPI Flash write bits
2306  *
2307  * Register|BitsName
2308  * --------|--------
2309  * FLASH_WRITE |FLASH_WRITE
2310  *
2311  * @param XQSPIx XQSPI instance
2312  * @param bits This parameter can be one of the following values:
2313  * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2314  * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2315  * @retval None
2316  */
2317 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
2318 {
2319  WRITE_REG(XQSPIx->QSPI.FLASH_WRITE, bits);
2320 }
2321 
2322 /**
2323  * @brief Get QSPI Flash write bits
2324  *
2325  * Register|BitsName
2326  * --------|--------
2327  * FLASH_WRITE |FLASH_WRITE
2328  *
2329  * @param XQSPIx XQSPI instance
2330  * @retval Returned Value can be one of the following values:
2331  * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2332  * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2333  */
2334 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
2335 {
2336  //GR551xx_C0 and future version.
2337  return READ_REG(XQSPIx->QSPI.FLASH_WRITE);
2338 }
2339 
2340 /**
2341  * @brief CS keeps valid while not reading
2342  * @note This bit should not be changed when XIP is ongoing.
2343  *
2344  * Register |BitsName
2345  * -------------------|--------
2346  * CS_IDLE_UNVLD_EN |XQSPI_QSPI_CS_IDLE_UNVLD_EN
2347  *
2348  * @param XQSPIx XQSPI instance
2349  * @retval None
2350  */
2351 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cs_idle_valid(xqspi_regs_t *XQSPIx)
2352 {
2353  CLEAR_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_CS_IDLE_UNVLD_EN);
2354 }
2355 
2356 /**
2357  * @brief CS keeps invalid while not reading
2358  * @note This bit should not be changed when XIP is ongoing.
2359  *
2360  * Register |BitsName
2361  * -------------------|--------
2362  * CS_IDLE_UNVLD_EN |XQSPI_QSPI_CS_IDLE_UNVLD_EN
2363  *
2364  * @param XQSPIx XQSPI instance
2365  * @retval None
2366  */
2367 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cs_idle_invalid(xqspi_regs_t *XQSPIx)
2368 {
2369  SET_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_CS_IDLE_UNVLD_EN);
2370 }
2371 
2372 
2373 /**
2374  * @brief enable 1st prefecth function
2375  * @note This bit should not be changed when XIP is ongoing.
2376  *
2377  * Register |BitsName
2378  * -------------------|--------
2379  * CS_IDLE_UNVLD_EN |XQSPI_QSPI_1ST_PRETETCH_DIS
2380  *
2381  * @param XQSPIx XQSPI instance
2382  * @retval None
2383  */
2384 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_1st_prefecth(xqspi_regs_t *XQSPIx)
2385 {
2386  CLEAR_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_1ST_PRETETCH_DIS);
2387 }
2388 
2389 /**
2390  * @brief disable 1st prefecth function
2391  * @note This bit should not be changed when XIP is ongoing.
2392  *
2393  * Register |BitsName
2394  * -------------------|--------
2395  * CS_IDLE_UNVLD_EN |XQSPI_QSPI_1ST_PRETETCH_DIS
2396  *
2397  * @param XQSPIx XQSPI instance
2398  * @retval None
2399  */
2400 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_1st_prefecth(xqspi_regs_t *XQSPIx)
2401 {
2402  SET_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_1ST_PRETETCH_DIS);
2403 }
2404 
2405 /**
2406  * @brief enable key_pulse to interrupt rd_data state
2407  * @note This bit should not be changed when XIP is ongoing.
2408  *
2409  * Register |BitsName
2410  * -------------------|--------
2411  * CS_IDLE_UNVLD_EN |XQSPI_QSPI_KEY_PULSE_DIS
2412  *
2413  * @param XQSPIx XQSPI instance
2414  * @retval None
2415  */
2416 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_key_pulse(xqspi_regs_t *XQSPIx)
2417 {
2418  CLEAR_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_KEY_PULSE_DIS);
2419 }
2420 
2421 /**
2422  * @brief disable key_pulse to interrupt rd_data state
2423  * @note This bit should not be changed when XIP is ongoing.
2424  *
2425  * Register |BitsName
2426  * -------------------|--------
2427  * CS_IDLE_UNVLD_EN |XQSPI_QSPI_KEY_PULSE_DIS
2428  *
2429  * @param XQSPIx XQSPI instance
2430  * @retval None
2431  */
2432 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_key_pulse(xqspi_regs_t *XQSPIx)
2433 {
2434  SET_BITS(XQSPIx->QSPI.CS_IDLE_UNVLD_EN, XQSPI_QSPI_KEY_PULSE_DIS);
2435 }
2436 
2437 /**
2438  * @brief Enable exflash power
2439  * @note This bit should not be changed when XIP is ongoing.
2440  *
2441  * Register|BitsName
2442  * --------|--------
2443  * PWR_RET01 | EFLASH_PAD_EN
2444  *
2445  * @retval None
2446  */
2447 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
2448 {
2449  SET_BITS(AON_CTL->FLASH_CACHE_CTRL1, AON_CTL_FLASH_CACHE_PAD_EN);
2450 }
2451 
2452 /**
2453  * @brief Disable exflash power
2454  * @note This bit should not be changed when XIP is ongoing.
2455  *
2456  * Register|BitsName
2457  * --------|--------
2458  * PWR_RET01 | EFLASH_PAD_EN
2459  *
2460  * @retval None
2461  */
2462 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
2463 {
2464  CLEAR_BITS(AON_CTL->FLASH_CACHE_CTRL1, AON_CTL_FLASH_CACHE_PAD_EN);
2465 }
2466 
2467 /**
2468  * @brief Check if exflash power is enabled
2469  *
2470  * Register|BitsName
2471  * --------|--------
2472  * PWR_RET01 | EFLASH_PAD_EN
2473  *
2474  * @retval State of bit (1 or 0).
2475  */
2476 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
2477 {
2478  return (READ_BITS(AON_CTL->FLASH_CACHE_CTRL1, AON_CTL_FLASH_CACHE_PAD_EN) == (AON_CTL_FLASH_CACHE_PAD_EN));
2479 }
2480 
2481 /**
2482  * @brief Set XQSPI serial clock
2483  *
2484  * Register|BitsName
2485  * --------|--------
2486  * PWR_RET01 | XF_SCK_CLK_SEL
2487  *
2488  * @param speed This parameter can be one of the following values:
2489  * @arg @ref LL_XQSPI_BAUD_RATE_64M
2490  * @arg @ref LL_XQSPI_BAUD_RATE_48M
2491  * @arg @ref LL_XQSPI_BAUD_RATE_32M
2492  * @arg @ref LL_XQSPI_BAUD_RATE_24M
2493  * @arg @ref LL_XQSPI_BAUD_RATE_16M
2494  * @retval None
2495  */
2496 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
2497 {
2498  MODIFY_REG(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL, speed);
2499 }
2500 
2501 /**
2502  * @brief Get XQSPI serial clock
2503  *
2504  * Register|BitsName
2505  * --------|--------
2506  * PWR_RET01 | XF_SCK_CLK_SEL
2507  *
2508  * @retval Returned Value can be one of the following values:
2509  * @arg @ref LL_XQSPI_BAUD_RATE_64M
2510  * @arg @ref LL_XQSPI_BAUD_RATE_48M
2511  * @arg @ref LL_XQSPI_BAUD_RATE_32M
2512  * @arg @ref LL_XQSPI_BAUD_RATE_24M
2513  * @arg @ref LL_XQSPI_BAUD_RATE_16M
2514  */
2515 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
2516 {
2517  return (uint32_t)(READ_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_SCK_CLK_SEL));
2518 }
2519 
2520 /**
2521  * @brief Enable cache data retention.
2522  * @note This bit should not be changed when XIP is ongoing..
2523  *
2524  * Register|BitsName
2525  * --------|--------
2526  * PWR_RET01 | XF_TAG_RET
2527  *
2528  * @retval None
2529  */
2530 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
2531 {
2532  SET_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_TAG_RET);
2533 }
2534 
2535 /**
2536  * @brief Disable cache data retention.
2537  * @note This bit should not be changed when XIP is ongoing.
2538  *
2539  * Register|BitsName
2540  * --------|--------
2541  * PWR_RET01 | XF_TAG_RET
2542  *
2543  * @retval None
2544  */
2545 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
2546 {
2547  CLEAR_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_TAG_RET);
2548 }
2549 
2550 /**
2551  * @brief Check if tag memory retention is enabled
2552  *
2553  * Register|BitsName
2554  * --------|--------
2555  * PWR_RET01 | XF_TAG_RET
2556  *
2557  * @retval State of bit (1 or 0).
2558  */
2559 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
2560 {
2561  return (READ_BITS(AON_CTL->FLASH_CACHE_CTRL0, AON_CTL_FLASH_CACHE_XF_TAG_RET) == (AON_CTL_FLASH_CACHE_XF_TAG_RET));
2562 }
2563 
2564 /**
2565  * @brief Enable exflash power auto power up by hw
2566  * @note This bit should not be changed when XIP is ongoing.
2567  *
2568  * Register|BitsName
2569  * --------|--------
2570  * PWR_RET01 | EFLASH_PAD_EN
2571  *
2572  * @retval None
2573  */
2574 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_auto_power(void)
2575 {
2576  CLEAR_BITS(AON_CTL->FLASH_CACHE_CTRL1, AON_CTL_FLASH_CACHE_PAD_BYPASS);
2577 }
2578 
2579 /**
2580  * @brief Disable exflash power auto power up by hwr
2581  * @note This bit should not be changed when XIP is ongoing.
2582  *
2583  * Register|BitsName
2584  * --------|--------
2585  * PWR_RET01 | EFLASH_PAD_EN
2586  *
2587  * @retval None
2588  */
2589 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_auto_power(void)
2590 {
2591  SET_BITS(AON_CTL->FLASH_CACHE_CTRL1, AON_CTL_FLASH_CACHE_PAD_BYPASS);
2592 }
2593 
2594 /** @} */
2595 
2596 /** @defgroup XQSPI_LL_Init XQSPI Initialization and de-initialization functions
2597  * @{
2598  */
2599 
2600 /**
2601  * @brief De-initialize XQSPI registers (Registers restored to their default values).
2602  * @param XQSPIx XQSPI instance
2603  * @retval An error_status_t enumeration value:
2604  * - SUCCESS: XQSPI registers are de-initialized
2605  * - ERROR: XQSPI registers are not de-initialized
2606  */
2607 SECTION_RAM_CODE error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx);
2608 
2609 /**
2610  * @brief Initialize XQSPI registers according to the specified
2611  * parameters in default.
2612  * @param XQSPIx XQSPI instance
2613  * @param p_xqspi_init Pointer to a ll_xqspi_init_t structure that contains the configuration
2614  * information for the specified XQPSI peripheral.
2615  * @retval An error_status_t enumeration value:
2616  * - SUCCESS: XQSPI registers are initialized according to default
2617  * - ERROR: Problem occurred during XQSPI Registers initialization
2618  */
2619 SECTION_RAM_CODE error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init);
2620 
2621 /**
2622  * @brief Set each field of a @ref ll_xqspi_init_t type structure to default value.
2623  * @param p_xqspi_init Pointer to a @ref ll_xqspi_init_t structure
2624  * whose fields will be set to default values.
2625  * @retval None
2626  */
2627 void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init);
2628 
2629 /**
2630  * @brief Initialize XQSPI XIP HP mode according to the specified
2631  * parameters.
2632  * @param p_xqspi_hp_init Pointer to a @ref ll_xqspi_hp_init_t structure.
2633  * @retval None
2634  */
2635 SECTION_RAM_CODE void ll_xqspi_set_xip_hp(ll_xqspi_hp_init_t *p_xqspi_hp_init);
2636 /** @} */
2637 
2638 /** @} */
2639 
2640 #endif /* XQSPI */
2641 
2642 #ifdef __cplusplus
2643 }
2644 #endif
2645 
2646 #endif /* __GR533x_LL_XQSPI_H__ */
2647 
2648 /** @} */
2649 
2650 /** @} */
2651 
2652 /** @} */
ll_xqspi_set_qspi_datasize
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
Set data size.
Definition: gr533x_ll_xqspi.h:1801
ll_xqspi_is_active_qspi_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check active flag.
Definition: gr533x_ll_xqspi.h:1997
ll_xqspi_disable_xip
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
Disable XIP mode.
Definition: gr533x_ll_xqspi.h:1196
ll_xqspi_disable_exflash_auto_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_auto_power(void)
Disable exflash power auto power up by hwr.
Definition: gr533x_ll_xqspi.h:2589
ll_xqspi_is_enabled_cache
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
Check if cache function is enabled.
Definition: gr533x_ll_xqspi.h:454
ll_xqspi_cache_direct_map_enable
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_cache_direct_map_enable(xqspi_regs_t *XQSPIx)
Enable cache direct map function.
Definition: gr533x_ll_xqspi.h:470
ll_xqspi_get_cache_dbgbus
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
Get debugbus configurations signals.
Definition: gr533x_ll_xqspi.h:671
_ll_xqspi_hp_init_t::xqspi_hp_cmd
uint8_t xqspi_hp_cmd
Definition: gr533x_ll_xqspi.h:81
ll_xqspi_is_enabled_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
Check if continuous transfer mode is enabled.
Definition: gr533x_ll_xqspi.h:1731
ll_xqspi_init_t
struct _ll_xqspi_init_t ll_xqspi_init_t
XQSPI init structures definition.
ll_xqspi_set_xip_ss
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
Set slave select.
Definition: gr533x_ll_xqspi.h:899
ll_xqspi_get_qspi_data_order
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
Get serial data order.
Definition: gr533x_ll_xqspi.h:1686
ll_xqspi_is_enable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
Check if exflash power is enabled.
Definition: gr533x_ll_xqspi.h:2476
ll_xqspi_get_cache_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
Get cache status.
Definition: gr533x_ll_xqspi.h:766
ll_xqspi_is_enabled_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
Check if XIP interrupt is enabled.
Definition: gr533x_ll_xqspi.h:1244
_ll_xqspi_init_t::clock_polarity
uint32_t clock_polarity
Definition: gr533x_ll_xqspi.h:116
ll_xqspi_enable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
Enable cache data retention.
Definition: gr533x_ll_xqspi.h:2530
ll_xqspi_enable_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
Enable DMA mode.
Definition: gr533x_ll_xqspi.h:1549
ll_xqspi_qspi_transmit_data16
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
Write 16-bit in the data register.
Definition: gr533x_ll_xqspi.h:1346
ll_xqspi_set_cs_idle_invalid
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cs_idle_invalid(xqspi_regs_t *XQSPIx)
CS keeps invalid while not reading.
Definition: gr533x_ll_xqspi.h:2367
ll_xqspi_get_xip_cmd
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
Get read command.
Definition: gr533x_ll_xqspi.h:816
ll_xqspi_disable_xip_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
Disable high performance mode.
Definition: gr533x_ll_xqspi.h:863
ll_xqspi_get_cache_fifo
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
Get FIFO mode.
Definition: gr533x_ll_xqspi.h:602
_ll_xqspi_init_t::baud_rate
uint32_t baud_rate
Definition: gr533x_ll_xqspi.h:126
ll_xqspi_get_xip_ss
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
Get slave select.
Definition: gr533x_ll_xqspi.h:918
ll_xqspi_get_qspi_cpol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr533x_ll_xqspi.h:1615
ll_xqspi_disable_qspi
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
Disable QSPI.
Definition: gr533x_ll_xqspi.h:2284
ll_xqspi_enable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
Enable exflash power.
Definition: gr533x_ll_xqspi.h:2447
ll_xqspi_disable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
Disable cache data retention.
Definition: gr533x_ll_xqspi.h:2545
ll_xqspi_disable_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Disable continuous transfer extend mode.
Definition: gr533x_ll_xqspi.h:1761
ll_xqspi_set_qspi_cpha
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr533x_ll_xqspi.h:1634
ll_xqspi_get_it_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
Get XQSPI interrupt flags.
Definition: gr533x_ll_xqspi.h:2175
ll_xqspi_get_xip_addr_size
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
Get address bytes in command.
Definition: gr533x_ll_xqspi.h:1026
_ll_xqspi_init_t::data_order
uint32_t data_order
Definition: gr533x_ll_xqspi.h:111
ll_xqspi_enable_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Enable debug bus mux.
Definition: gr533x_ll_xqspi.h:687
ll_xqspi_is_enabled_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
Check if debug bus mux is enabled.
Definition: gr533x_ll_xqspi.h:718
ll_xqspi_cache_direct_map_is_enabled
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_cache_direct_map_is_enabled(xqspi_regs_t *XQSPIx)
Check if cache direct map function is enabled.
Definition: gr533x_ll_xqspi.h:503
ll_xqspi_enable_xip_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
Enable high performance mode.
Definition: gr533x_ll_xqspi.h:832
ll_xqspi_enable_key_pulse
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_key_pulse(xqspi_regs_t *XQSPIx)
enable key_pulse to interrupt rd_data state
Definition: gr533x_ll_xqspi.h:2416
ll_xqspi_is_enabled_cache_flush
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
Check if tag memory flush is enabled.
Definition: gr533x_ll_xqspi.h:550
ll_xqspi_set_flash_write
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
Set QSPI Flash write bits.
Definition: gr533x_ll_xqspi.h:2317
_ll_xqspi_init_t::cache_mode
uint32_t cache_mode
Definition: gr533x_ll_xqspi.h:96
ll_xqspi_disable_cache_dbgmux
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
Disable debug bus mux.
Definition: gr533x_ll_xqspi.h:703
ll_xqspi_get_xip_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
Get XIP status.
Definition: gr533x_ll_xqspi.h:1228
ll_xqspi_enable_qspi_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Enable interrupt.
Definition: gr533x_ll_xqspi.h:2112
ll_xqspi_set_cache_dbgbus
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
Set debugbus configurations signals.
Definition: gr533x_ll_xqspi.h:656
ll_xqspi_is_enabled_xip_hp
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
Check if high performance mode is enabled.
Definition: gr533x_ll_xqspi.h:878
_ll_xqspi_hp_init_t
XQSPI High Performance mode init structures definition.
Definition: gr533x_ll_xqspi.h:77
ll_xqspi_hp_init_t
struct _ll_xqspi_hp_init_t ll_xqspi_hp_init_t
XQSPI High Performance mode init structures definition.
ll_xqspi_enable_1st_prefecth
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_1st_prefecth(xqspi_regs_t *XQSPIx)
enable 1st prefecth function
Definition: gr533x_ll_xqspi.h:2384
ll_xqspi_disable_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
Disable inhibt data input to RX FIFO.
Definition: gr533x_ll_xqspi.h:1854
ll_xqspi_set_xip_hp_cmd
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set high performance command.
Definition: gr533x_ll_xqspi.h:1080
ll_xqspi_enable_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Enable continuous transfer mode.
Definition: gr533x_ll_xqspi.h:1701
ll_xqspi_struct_init
void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init)
Set each field of a ll_xqspi_init_t type structure to default value.
ll_xqspi_get_qspi_rft
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
Get RX FIFO threshold level.
Definition: gr533x_ll_xqspi.h:1489
ll_xqspi_enable_xip
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
Enable XIP mode.
Definition: gr533x_ll_xqspi.h:1181
ll_xqspi_set_cs_idle_valid
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cs_idle_valid(xqspi_regs_t *XQSPIx)
CS keeps valid while not reading.
Definition: gr533x_ll_xqspi.h:2351
ll_xqspi_get_qspi_wait
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
Get master inter-transfer delay.
Definition: gr533x_ll_xqspi.h:2253
ll_xqspi_is_enabled_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to TX FIFO is enabled.
Definition: gr533x_ll_xqspi.h:1914
ll_xqspi_is_qspi_it_flag
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Check interrupt flag.
Definition: gr533x_ll_xqspi.h:2200
ll_xqspi_qspi_receive_data8
SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
Read 8 bits in the data register.
Definition: gr533x_ll_xqspi.h:1377
ll_xqspi_get_xip_dummy_hp
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
Get dummy cycles in high performance end.
Definition: gr533x_ll_xqspi.h:1166
ll_xqspi_is_enabled_qspi_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Check if interrupt is enabled.
Definition: gr533x_ll_xqspi.h:2155
ll_xqspi_is_enabled_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
Check if DMA mode is enabled.
Definition: gr533x_ll_xqspi.h:1579
ll_xqspi_is_enabled_xip
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
Check if XIP mode is enabled.
Definition: gr533x_ll_xqspi.h:1212
ll_xqspi_get_req_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt request.
Definition: gr533x_ll_xqspi.h:1276
_ll_xqspi_init_t::cache_direct_map_en
uint32_t cache_direct_map_en
Definition: gr533x_ll_xqspi.h:131
ll_xqspi_set_cache_clk_force_en
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_clk_force_en(xqspi_regs_t *XQSPIx)
Set cache gating dynamically.
Definition: gr533x_ll_xqspi.h:565
ll_xqspi_enable_qspi
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
Enable QSPI.
Definition: gr533x_ll_xqspi.h:2269
ll_xqspi_get_flash_write
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
Get QSPI Flash write bits.
Definition: gr533x_ll_xqspi.h:2334
ll_xqspi_disable_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
Disable dummy cycles.
Definition: gr533x_ll_xqspi.h:1519
ll_xqspi_set_qspi_tft
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set TX FIFO threshold level.
Definition: gr533x_ll_xqspi.h:1428
ll_xqspi_get_qspi_frf
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
Get frame format.
Definition: gr533x_ll_xqspi.h:1952
ll_xqspi_is_enabled_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
Check if dummy cycles is enabled.
Definition: gr533x_ll_xqspi.h:1534
ll_xqspi_init
SECTION_RAM_CODE error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init)
Initialize XQSPI registers according to the specified parameters in default.
ll_xqspi_enable_xip_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt enable.
Definition: gr533x_ll_xqspi.h:1292
ll_xqspi_disable_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
Disable inhibt data output to TX FIFO.
Definition: gr533x_ll_xqspi.h:1899
ll_xqspi_is_enabled_qspi
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
Check if QSPI is enabled.
Definition: gr533x_ll_xqspi.h:2299
ll_xqspi_set_xip_cpha
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
Set clock phase.
Definition: gr533x_ll_xqspi.h:937
ll_xqspi_clear_qspi_flag
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
Clear interrupt flag.
Definition: gr533x_ll_xqspi.h:2222
ll_xqspi_get_qspi_sspol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
Get slave select output polarity.
Definition: gr533x_ll_xqspi.h:2060
ll_xqspi_qspi_transmit_data32
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
Write 32-bit in the data register.
Definition: gr533x_ll_xqspi.h:1362
ll_xqspi_get_qspi_speed
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
Get XQSPI serial clock.
Definition: gr533x_ll_xqspi.h:2515
ll_xqspi_disable_1st_prefecth
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_1st_prefecth(xqspi_regs_t *XQSPIx)
disable 1st prefecth function
Definition: gr533x_ll_xqspi.h:2400
ll_xqspi_is_enable_cache_retention
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
Check if tag memory retention is enabled.
Definition: gr533x_ll_xqspi.h:2559
ll_xqspi_disable_exflash_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
Disable exflash power.
Definition: gr533x_ll_xqspi.h:2462
ll_xqspi_get_cache_hitmiss
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
Get HIT/MISS mode.
Definition: gr533x_ll_xqspi.h:639
_ll_xqspi_init_t::mode
uint32_t mode
Definition: gr533x_ll_xqspi.h:93
ll_xqspi_set_qspi_speed
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
Set XQSPI serial clock.
Definition: gr533x_ll_xqspi.h:2496
_ll_xqspi_hp_init_t::xqspi_hp_enable
uint8_t xqspi_hp_enable
Definition: gr533x_ll_xqspi.h:78
ll_xqspi_disable_qspi_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
Disable interrupt.
Definition: gr533x_ll_xqspi.h:2134
ll_xqspi_disable_qspi_dma
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
Disable DMA mode.
Definition: gr533x_ll_xqspi.h:1564
ll_xqspi_qspi_receive_data32
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
Read 32 bits in the data register.
Definition: gr533x_ll_xqspi.h:1407
ll_xqspi_enable_exflash_auto_power
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_auto_power(void)
Enable exflash power auto power up by hw.
Definition: gr533x_ll_xqspi.h:2574
ll_xqspi_enable_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Enable continuous transfer extend mode.
Definition: gr533x_ll_xqspi.h:1746
ll_xqspi_set_xip_cpol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr533x_ll_xqspi.h:973
ll_xqspi_get_xip_cpol
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
Get clock polarity.
Definition: gr533x_ll_xqspi.h:990
ll_xqspi_enable_cache
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
Enable cache function.
Definition: gr533x_ll_xqspi.h:421
ll_xqspi_is_enabled_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
Check if inhibt data input to RX FIFO is enabled.
Definition: gr533x_ll_xqspi.h:1869
ll_xqspi_disable_xip_it
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
Set XIP interrupt disable.
Definition: gr533x_ll_xqspi.h:1308
ll_xqspi_qspi_receive_data16
SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
Read 16 bits in the data register.
Definition: gr533x_ll_xqspi.h:1392
ll_xqspi_get_qspi_status
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
Get QSPI status.
Definition: gr533x_ll_xqspi.h:1974
ll_xqspi_get_xip_cpha
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr533x_ll_xqspi.h:954
ll_xqspi_set_xip_addr_size
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
Set address bytes in command.
Definition: gr533x_ll_xqspi.h:1009
ll_xqspi_set_qspi_frf
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
Set frame format.
Definition: gr533x_ll_xqspi.h:1934
ll_xqspi_set_qspi_wait
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
Set master inter-transfer delay.
Definition: gr533x_ll_xqspi.h:2238
ll_xqspi_is_enabled_qspi_contxfer_extend
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
Check if continuous transfer extend mode is enabled.
Definition: gr533x_ll_xqspi.h:1776
ll_xqspi_set_xip_endian
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
Set endian in reading data.
Definition: gr533x_ll_xqspi.h:1045
ll_xqspi_set_qspi_data_order
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
Set serial data order.
Definition: gr533x_ll_xqspi.h:1669
ll_xqspi_enable_qspi_ssout
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Enable slave select output.
Definition: gr533x_ll_xqspi.h:2013
_ll_xqspi_init_t
XQSPI init structures definition.
Definition: gr533x_ll_xqspi.h:92
ll_xqspi_disable_qspi_ssout
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
Disable slave select output.
Definition: gr533x_ll_xqspi.h:2029
ll_xqspi_set_cache_hitmiss
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
Set HIT/MISS mode.
Definition: gr533x_ll_xqspi.h:621
ll_xqspi_enable_inhibt_tx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
Enable inhibt data output to TX FIFO.
Definition: gr533x_ll_xqspi.h:1884
ll_xqspi_disable_qspi_contxfer
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
Disable continuous transfer mode.
Definition: gr533x_ll_xqspi.h:1716
ll_xqspi_soft_rst_req
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_soft_rst_req(xqspi_regs_t *XQSPIx)
Enable xqspi soft response request.
Definition: gr533x_ll_xqspi.h:847
_ll_xqspi_init_t::cache_flush
uint32_t cache_flush
Definition: gr533x_ll_xqspi.h:134
ll_xqspi_set_cache_fifo
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
Set FIFO mode.
Definition: gr533x_ll_xqspi.h:584
_ll_xqspi_init_t::clock_phase
uint32_t clock_phase
Definition: gr533x_ll_xqspi.h:121
ll_xqspi_get_flag_xip_it
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
Get XIP interrupt flag.
Definition: gr533x_ll_xqspi.h:1260
_ll_xqspi_init_t::read_cmd
uint32_t read_cmd
Definition: gr533x_ll_xqspi.h:101
ll_xqspi_get_cache_hitcount
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
Get hit counter.
Definition: gr533x_ll_xqspi.h:734
ll_xqspi_get_xip_hp_cmd
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
Get high performance command.
Definition: gr533x_ll_xqspi.h:1095
ll_xqspi_get_cache_misscount
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
Get miss counter.
Definition: gr533x_ll_xqspi.h:750
ll_xqspi_set_qspi_cpol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
Set clock polarity.
Definition: gr533x_ll_xqspi.h:1598
ll_xqspi_get_qspi_tx_fifo_level
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO Transmission Level.
Definition: gr533x_ll_xqspi.h:2075
ll_xqspi_set_xip_dummy_hp
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in high performance end.
Definition: gr533x_ll_xqspi.h:1151
ll_xqspi_get_qspi_rx_fifo_level
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
Get FIFO reception Level.
Definition: gr533x_ll_xqspi.h:2090
ll_xqspi_enable_cache_flush
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
Enable tag memory flush.
Definition: gr533x_ll_xqspi.h:519
ll_xqspi_qspi_transmit_data8
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
Write 8-bit in the data register.
Definition: gr533x_ll_xqspi.h:1330
ll_xqspi_get_qspi_cpha
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
Get clock phase.
Definition: gr533x_ll_xqspi.h:1651
ll_xqspi_set_xip_hp
SECTION_RAM_CODE void ll_xqspi_set_xip_hp(ll_xqspi_hp_init_t *p_xqspi_hp_init)
Initialize XQSPI XIP HP mode according to the specified parameters.
ll_xqspi_enable_qspi_dummy
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
Enable dummy cycles.
Definition: gr533x_ll_xqspi.h:1504
ll_xqspi_set_xip_dummycycles
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
Set dummy cycles in command.
Definition: gr533x_ll_xqspi.h:1116
ll_xqspi_disable_cache_flush
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
Disable tag memory flush.
Definition: gr533x_ll_xqspi.h:535
ll_xqspi_set_qspi_sspol
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
Set slave select output polarity.
Definition: gr533x_ll_xqspi.h:2045
ll_xqspi_enable_inhibt_rx
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
Enable inhibt data input to RX FIFO.
Definition: gr533x_ll_xqspi.h:1839
ll_xqspi_set_xip_cmd
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
Set read command.
Definition: gr533x_ll_xqspi.h:795
ll_xqspi_get_xip_dummycycles
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
Get dummy cycles in command.
Definition: gr533x_ll_xqspi.h:1135
_ll_xqspi_hp_init_t::xqspi_hp_end_dummy
uint8_t xqspi_hp_end_dummy
Definition: gr533x_ll_xqspi.h:83
ll_xqspi_get_xip_endian
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
Get endian in reading data.
Definition: gr533x_ll_xqspi.h:1062
ll_xqspi_disable_cache
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
Disable cache function.
Definition: gr533x_ll_xqspi.h:438
ll_xqspi_get_qspi_tft
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
Get TX FIFO threshold level.
Definition: gr533x_ll_xqspi.h:1448
ll_xqspi_get_qspi_datasize
SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
Get data size.
Definition: gr533x_ll_xqspi.h:1824
ll_xqspi_deinit
SECTION_RAM_CODE error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx)
De-initialize XQSPI registers (Registers restored to their default values).
ll_xqspi_cache_direct_map_disable
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_cache_direct_map_disable(xqspi_regs_t *XQSPIx)
Disable cache direct map function.
Definition: gr533x_ll_xqspi.h:487
ll_xqspi_disable_key_pulse
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_key_pulse(xqspi_regs_t *XQSPIx)
disable key_pulse to interrupt rd_data state
Definition: gr533x_ll_xqspi.h:2432
ll_xqspi_set_qspi_rft
SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
Set RX FIFO threshold level.
Definition: gr533x_ll_xqspi.h:1469
_ll_xqspi_init_t::data_size
uint32_t data_size
Definition: gr533x_ll_xqspi.h:106
_ll_xqspi_init_t::hp_init
ll_xqspi_hp_init_t hp_init
Definition: gr533x_ll_xqspi.h:137