SRAM
The main Static Random Access Memory (SRAM) is comprised of an on-chip static RAM totaling up to 512 KB. The main SRAM is implemented as several SRAM instances to allow for more control of power usage when less SRAM is required (4 x 32 KB instances, 2 x 64 KB instances, 2 x 128 KB instances). Each SRAM instance has one or two independent power switches, which control SRAM in three states: full power, retention power, and power off. The relationship between SRAM instances and power domains is shown in 表 35.
Introduction
Although always contiguous on all GR5526 devices, the SRAM instances are divided between eight AHB matrix ports. This allows user programs to potentially achieve better performance by dividing RAM usage among the ports. For example, simultaneous access to SRAM0 by the CPU and SRAM1 by the system DMA controller does not result in any bus stalls for either master. When multiple masters access the same SRAM, GR5526 uses round-robin scheduling to configure the priorities of multiple hosts, ensuring the fairness of multi-master access.
Generally, the CPU will read or write all peripheral data at some point, even when all such data is read from or sent to a peripheral by DMA. Therefore, minimizing stalls is likely to involve putting data to/from different peripherals in RAM on each port.
Alternatively, sequences of data from the same peripheral can be alternated between RAM on each port. This can be helpful if DMA fills or empties a RAM buffer, and then signals the CPU before proceeding with a second buffer. The CPU will then tend to access the data while the DMA is using RAM on the other port.
At the same time, according to Memory Map, GR5526 provides an Aliasing Memory with the start address of 0x0010_0000 and 0x3000 0000 for the RAM with the start address of 0x2000 0000.
- The start address of the area is 0x2000 0000, which supports bit-segment operations, and its corresponding bit-segment start address is 0x2200 0000.
- Due to the characteristics of the Cortex®-M4F bus architecture, the access efficiency of the area with the start address of 0x0010 0000 is higher than that of other areas, so the running address of the RAM_CODE executable code is within the address range of the 0x0010_0000 area, which can speed up the operation. RW, ZI, HEAP, and STACK use RAM in the 0x2000 0000 area.
