SRAM Power Control
The current system supports three SRAM power modes:
- Full power
SRAM can provide full-speed read-write function. This mode is only used when MCU is powered on.
- Retention power
When the system enters the sleep mode, the SRAM can enter the retention state during which data can be retained. Read and write operations are not available in this mode.
- Power off
In this mode, all data will be cleared, and the SRAM will enter the power off state. If users need to control the power supply of SRAM, it is recommended to use the standard functions in the SDK. The SDK also provides the automatic management function of SRAM. This function will be automatically managed according to the RAM used by user programs.
The main Static Random Access Memory (SRAM) is comprised of an on-chip static RAM totaling up to 512 KB. The main SRAM is implemented as several SRAM instances to allow for more control of power usage when less SRAM is required (4 x 32 KB instances, 2 x 64 KB instances, 2 x 128 KB instances). Developers can turn off the redundant SRAM instances or set the active SRAM instances as retention (cannot write or read) in deep sleep mode in order to reduce the power consumption of the SRAM during sleep.
There are 11 power domains for the SRAM, from pd_mcu_00 to pd_mcu_10. The relationship between the SRAM instances and the power domains is shown in 表 35.
| Instance | Access Offset | Size (KB) | Power Domain | Cell Size (KB) | |
|---|---|---|---|---|---|
| Low | High | ||||
| SRAM0 | 0x00000000 | 0x00007FFF | 32 | pd_mcu_00 | 16 |
| pd_mcu_01 | 16 | ||||
| SRAM1 | 0x00008000 | 0x0000FFFF | 32 | pd_mcu_02 | 32 |
| SRAM2 | 0x00010000 | 0x0001FFFF | 64 | pd_mcu_03 | 32 |
| pd_mcu_04 | 64 | ||||
| SRAM3 | 0x00020000 | 0x0002FFFF | 64 | ||
| pd_mcu_05 | 64 | ||||
| SRAM4 | 0x00030000 | 0x0004FFFF | 128 | ||
| pd_mcu_06 | 64 | ||||
| pd_mcu_07 | 64 | ||||
| SRAM5 | 0x00050000 | 0x0006FFFF | 128 | ||
| pd_mcu_08 | 64 | ||||
| pd_mcu_09 | 64 | ||||
| SRAM6 | 0x00070000 | 0x00077FFF | 32 | ||
| SRAM7 | 0x00078000 | 0x0007FFFF | 32 | pd_mcu_10 | 32 |
The SRAM power domain in the wake-up phase can be set through MEM_PWR_WKUP0. The SRAM power domain in the sleep phase can be set through MEM_PWR_SLP0. MEM_PWR_APPLY is used to apply the configuration of MEM_PWR_WKUP0 or MEM_PWR_SLP0. The current working state of the SRAM power domain can be obtained by reading MEM_PWR_STAT0. However, it cannot be read when MEM_PWR_APPLY is busy.
Since the SRAM instances and the power domains do not correspond one-to-one, developers need to configure specific registers according to their relationship shown in 表 35. Normally, the first 24 KB of the SRAM0 instance is reserved for Bootloader and BLE protocol stack. Therefore, pd_mcu_00 and pd_mcu_01 should be set in full power in the wake-up phase, and should be set in retention in the sleep phase. For detailed instructions on usage of SRAM, refer to GR5526 Developer Guide.
Registers
MEM_PWR_SLP0
- Address: 0xA000A480
- Reset Value: 0x003FFFFF
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:22 | RSVD | R | Reserved bits | |
| 21:20 | PD_MCU_10_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
| 19:18 | PD_MCU_9_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
| 17:16 | PD_MCU_8_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
| 15:14 | PD_MCU_7_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
| 13:12 | PD_MCU_6_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
| 11:10 | PD_MCU_5_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
| 9:8 | PD_MCU_4_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
| 7:6 | PD_MCU_3_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
| 5:4 | PD_MCU_2_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
| 3:2 | PD_MCU_1_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
| 1:0 | PD_MCU_0_SLP_PWR_SET | RW | 0x3 |
Memory power states that be loaded in sleep phase Value:
|
MEM_PWR_WKUP0
- Address: 0xA000A488
- Reset Value: 0x002AAAAA
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:22 | RSVD | R | Reserved bits | |
| 21:20 | PD_MCU_10_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
| 19:18 | PD_MCU_9_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
| 17:16 | PD_MCU_8_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
| 15:14 | PD_MCU_7_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
| 13:12 | PD_MCU_6_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
| 11:10 | PD_MCU_5_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
| 9:8 | PD_MCU_4_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
| 7:6 | PD_MCU_3_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
| 5:4 | PD_MCU_2_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
| 3:2 | PD_MCU_1_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
| 1:0 | PD_MCU_0_WKUP_PWR_SET | RW | 0x2 |
Memory power states that be loaded in wakeup phase Value:
|
MEM_PWR_APPLY
- Address: 0xA000A490
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:17 | RSVD | R | Reserved bits | |
| 16 | MEM_PWR_APPLY_BUSY | R | 0x0 | When the bit is set to 1, writing MEM_PWR_APPLY_MAN would not take any effect. |
| 15:1 | RSVD | R | Reserved bits | |
| 0 | MEM_PWR_APPLY_MAN | W | 0x0 | Write 1 to apply the memory settings manually. |
MEM_PWR_STAT0
- Address: 0xA000A498
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:22 | RSVD | R | Reserved bits | |
| 21:20 | PD_MCU_10_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
| 19:18 | PD_MCU_9_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
| 17:16 | PD_MCU_8_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
| 15:14 | PD_MCU_7_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
| 13:12 | PD_MCU_6_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
| 11:10 | PD_MCU_5_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
| 9:8 | PD_MCU_4_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
| 7:6 | PD_MCU_3_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
| 5:4 | PD_MCU_2_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
| 3:2 | PD_MCU_1_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
| 1:0 | PD_MCU_0_PWR_STAT | R | 0x0 |
Memory power states. Do NOT read when MEM_PWR_APPLY is busy. Value:
|
